On 14/04/2021 13:26, Ruifeng Zhang wrote:
> Dietmar Eggemann 于2021年4月14日周三 下午5:43写道:
>>
>> On 13/04/2021 15:26, Ruifeng Zhang wrote:
>>> Thanks for your review. Patch-v2 that solve the capacity issue will be
>>> uploaded as soon as possible. : )
>>>
>>> Valentin Schneider 于2021年4月13日周二 下午7:40写道:
Dietmar Eggemann 于2021年4月14日周三 下午5:43写道:
>
> On 13/04/2021 15:26, Ruifeng Zhang wrote:
> > Thanks for your review. Patch-v2 that solve the capacity issue will be
> > uploaded as soon as possible. : )
> >
> > Valentin Schneider 于2021年4月13日周二 下午7:40写道:
> >>
> >> On 13/04/21 14:13, Ruifeng Zhang wro
On 13/04/2021 15:26, Ruifeng Zhang wrote:
> Thanks for your review. Patch-v2 that solve the capacity issue will be
> uploaded as soon as possible. : )
>
> Valentin Schneider 于2021年4月13日周二 下午7:40写道:
>>
>> On 13/04/21 14:13, Ruifeng Zhang wrote:
>>> Valentin Schneider 于2021年4月12日周一 下午11:33写道:
Thanks for your review. Patch-v2 that solve the capacity issue will be
uploaded as soon as possible. : )
Valentin Schneider 于2021年4月13日周二 下午7:40写道:
>
> On 13/04/21 14:13, Ruifeng Zhang wrote:
> > Valentin Schneider 于2021年4月12日周一 下午11:33写道:
> >> I'm not fluent at all in armv7 (or most aarch32 com
On 13/04/21 14:13, Ruifeng Zhang wrote:
> Valentin Schneider 于2021年4月12日周一 下午11:33写道:
>> I'm not fluent at all in armv7 (or most aarch32 compat mode stuff), but
>> I couldn't find anything about MPIDR format differences:
>>
>> DDI 0487G.a G8.2.113
>> """
>> AArch32 System register MPIDR bits
Dietmar Eggemann 于2021年4月12日周一 下午8:40写道:
>
> On 12/04/2021 14:20, Ruifeng Zhang wrote:
> > Valentin Schneider 于2021年4月12日周一 下午7:32写道:
> >>
> >>
> >> Hi,
> >>
> >> On 12/04/21 15:08, Ruifeng Zhang wrote:
> >>> From: Ruifeng Zhang
> >>>
> >>> The arm topology still parse from the MPIDR, but it is
Valentin Schneider 于2021年4月12日周一 下午11:33写道:
>
> On 12/04/21 20:20, Ruifeng Zhang wrote:
> > There is a armv8.3 cpu which should work normally both on aarch64 and
> > aarch32.
> > The MPIDR has been written to the chip register in armv8.3 format.
> > For example,
> > core0: 8000
> > co
On 12/04/21 20:20, Ruifeng Zhang wrote:
> There is a armv8.3 cpu which should work normally both on aarch64 and aarch32.
> The MPIDR has been written to the chip register in armv8.3 format.
> For example,
> core0: 8000
> core1: 8100
> core2: 8200
> ...
>
> Its cp
On 12/04/2021 14:20, Ruifeng Zhang wrote:
> Valentin Schneider 于2021年4月12日周一 下午7:32写道:
>>
>>
>> Hi,
>>
>> On 12/04/21 15:08, Ruifeng Zhang wrote:
>>> From: Ruifeng Zhang
>>>
>>> The arm topology still parse from the MPIDR, but it is incomplete. When
>>> the armv8.3 cpu runs in aarch32 mode, it w
Valentin Schneider 于2021年4月12日周一 下午7:32写道:
>
>
> Hi,
>
> On 12/04/21 15:08, Ruifeng Zhang wrote:
> > From: Ruifeng Zhang
> >
> > The arm topology still parse from the MPIDR, but it is incomplete. When
> > the armv8.3 cpu runs in aarch32 mode, it will parse out the wrong topology.
> >
> > armv7 (
Hi,
On 12/04/21 15:08, Ruifeng Zhang wrote:
> From: Ruifeng Zhang
>
> The arm topology still parse from the MPIDR, but it is incomplete. When
> the armv8.3 cpu runs in aarch32 mode, it will parse out the wrong topology.
>
> armv7 (A7) mpidr is:
> [11:8] [7:2] [1:0]
> cluster res
From: Ruifeng Zhang
The arm topology still parse from the MPIDR, but it is incomplete. When
the armv8.3 cpu runs in aarch32 mode, it will parse out the wrong topology.
armv7 (A7) mpidr is:
[11:8] [7:2] [1:0]
cluster reservedcpu
armv8.3 (A55) mpidr is:
[23:16] [15:8]
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