On 05/16/2015 01:12 AM, Benson Leung wrote:
On Fri, May 15, 2015 at 5:07 AM, Bill Huang wrote:
This fixes two things.
- Read the correct IDDQ register
- Check the correct IDDQ bit position
Signed-off-by: Bill Huang
Reviewed-by: Benson Leung
By the way, does it also make sense to do the
On 05/16/2015 01:12 AM, Benson Leung wrote:
On Fri, May 15, 2015 at 5:07 AM, Bill Huang bilhu...@nvidia.com wrote:
This fixes two things.
- Read the correct IDDQ register
- Check the correct IDDQ bit position
Signed-off-by: Bill Huang bilhu...@nvidia.com
Reviewed-by: Benson Leung
On Fri, May 15, 2015 at 5:07 AM, Bill Huang wrote:
> This fixes two things.
>
> - Read the correct IDDQ register
> - Check the correct IDDQ bit position
>
> Signed-off-by: Bill Huang
Reviewed-by: Benson Leung
By the way, does it also make sense to do the same thing for
This fixes two things.
- Read the correct IDDQ register
- Check the correct IDDQ bit position
Signed-off-by: Bill Huang
---
drivers/clk/tegra/clk-pll.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index
This fixes two things.
- Read the correct IDDQ register
- Check the correct IDDQ bit position
Signed-off-by: Bill Huang bilhu...@nvidia.com
---
drivers/clk/tegra/clk-pll.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c
On Fri, May 15, 2015 at 5:07 AM, Bill Huang bilhu...@nvidia.com wrote:
This fixes two things.
- Read the correct IDDQ register
- Check the correct IDDQ bit position
Signed-off-by: Bill Huang bilhu...@nvidia.com
Reviewed-by: Benson Leung ble...@chromium.org
By the way, does it also make
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