Re: [PATCH 1/2] PCI/ASPM: Disable ASPM until its LTR and L1ss state is restored

2021-01-14 Thread Victor Ding
On Thu, Jan 14, 2021 at 7:54 AM Bjorn Helgaas wrote: > > On Wed, Jan 13, 2021 at 01:16:05PM +1100, Victor Ding wrote: > > On Wed, Jan 13, 2021 at 9:32 AM Bjorn Helgaas wrote: > > > On Tue, Jan 12, 2021 at 04:02:04AM +, Victor Ding wrote: > > > > Right after powering up, the device may have

Re: [PATCH 1/2] PCI/ASPM: Disable ASPM until its LTR and L1ss state is restored

2021-01-13 Thread Bjorn Helgaas
On Wed, Jan 13, 2021 at 01:16:05PM +1100, Victor Ding wrote: > On Wed, Jan 13, 2021 at 9:32 AM Bjorn Helgaas wrote: > > On Tue, Jan 12, 2021 at 04:02:04AM +, Victor Ding wrote: > > > Right after powering up, the device may have ASPM enabled; however, > > > its LTR and/or L1ss controls may not

Re: [PATCH 1/2] PCI/ASPM: Disable ASPM until its LTR and L1ss state is restored

2021-01-12 Thread Victor Ding
Hi Bjorn, On Wed, Jan 13, 2021 at 9:32 AM Bjorn Helgaas wrote: > > Hi Victor, > > Thanks for the patch. Improving suspend/resume performance is always > a good thing! > > On Tue, Jan 12, 2021 at 04:02:04AM +, Victor Ding wrote: > > Right after powering up, the device may have ASPM enabled;

Re: [PATCH 1/2] PCI/ASPM: Disable ASPM until its LTR and L1ss state is restored

2021-01-12 Thread Bjorn Helgaas
Hi Victor, Thanks for the patch. Improving suspend/resume performance is always a good thing! On Tue, Jan 12, 2021 at 04:02:04AM +, Victor Ding wrote: > Right after powering up, the device may have ASPM enabled; however, > its LTR and/or L1ss controls may not be in the desired states;

[PATCH 1/2] PCI/ASPM: Disable ASPM until its LTR and L1ss state is restored

2021-01-11 Thread Victor Ding
Right after powering up, the device may have ASPM enabled; however, its LTR and/or L1ss controls may not be in the desired states; hence, the device may enter L1.2 undesirably and cause resume performance penalty. This is especially problematic if ASPM related control registers are modified before