Re: [PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates

Quoting Eric Anholt (2016-02-15 19:03:57) > Our dividers weren't being set successfully because CM_PASSWORD wasn't > included in the register write. It looks easier to just compute the > divider to write ourselves than to update clk-divider for the ability > to OR in some arbitrary bits on write.

Re: [PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates

Quoting Eric Anholt (2016-02-15 19:03:57) > Our dividers weren't being set successfully because CM_PASSWORD wasn't > included in the register write. It looks easier to just compute the > divider to write ourselves than to update clk-divider for the ability > to OR in some arbitrary bits on write.

[PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates

Our dividers weren't being set successfully because CM_PASSWORD wasn't included in the register write. It looks easier to just compute the divider to write ourselves than to update clk-divider for the ability to OR in some arbitrary bits on write. Fixes about half of the video modes on my HDMI

[PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates

Our dividers weren't being set successfully because CM_PASSWORD wasn't included in the register write. It looks easier to just compute the divider to write ourselves than to update clk-divider for the ability to OR in some arbitrary bits on write. Fixes about half of the video modes on my HDMI