Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller

2019-04-03 Thread Rob Herring
On Mon, Apr 1, 2019 at 11:36 AM James Morse wrote: > > Hi Rob, > > On 29/03/2019 14:11, Rob Herring wrote: > > On Thu, Mar 28, 2019 at 1:47 PM James Morse wrote: > >> On 28/03/2019 13:16, Rob Herring wrote: > >>> On Tue, Mar 12, 2019 at 02:51:00PM +0530, Yash Shah wrote: > DT documentation

Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller

2019-04-03 Thread Rob Herring
On Fri, Mar 29, 2019 at 3:24 PM Borislav Petkov wrote: > > On Fri, Mar 29, 2019 at 02:41:05PM -0500, Rob Herring wrote: > > DT dictates aligning with what the h/w looks like which has little to > > do with OS driver design. > > Ok, then, where does this goal for doing a driver or compilation unit

Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller

2019-04-01 Thread James Morse
Hi Rob, On 29/03/2019 14:11, Rob Herring wrote: > On Thu, Mar 28, 2019 at 1:47 PM James Morse wrote: >> On 28/03/2019 13:16, Rob Herring wrote: >>> On Tue, Mar 12, 2019 at 02:51:00PM +0530, Yash Shah wrote: DT documentation for L2 cache controller added. diff --git

Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller

2019-03-29 Thread Borislav Petkov
On Fri, Mar 29, 2019 at 02:41:05PM -0500, Rob Herring wrote: > DT dictates aligning with what the h/w looks like which has little to > do with OS driver design. Ok, then, where does this goal for doing a driver or compilation unit per IP block come from? Because everytime an ARM EDAC driver pops

Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller

2019-03-29 Thread Rob Herring
On Fri, Mar 29, 2019 at 9:27 AM Borislav Petkov wrote: > > On Fri, Mar 29, 2019 at 09:11:24AM -0500, Rob Herring wrote: > > I honestly don't understand the issue with EDAC is here. > > The EDAC core supports only one driver and if you need to load more, you > need to dance around that. > > Also,

Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller

2019-03-29 Thread Borislav Petkov
On Fri, Mar 29, 2019 at 09:11:24AM -0500, Rob Herring wrote: > I honestly don't understand the issue with EDAC is here. The EDAC core supports only one driver and if you need to load more, you need to dance around that. Also, if those drivers need to talk amongst each other, then they need to

Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller

2019-03-29 Thread Rob Herring
On Thu, Mar 28, 2019 at 1:47 PM James Morse wrote: > > Hi Rob, Yash, > > On 28/03/2019 13:16, Rob Herring wrote: > > On Tue, Mar 12, 2019 at 02:51:00PM +0530, Yash Shah wrote: > >> DT documentation for L2 cache controller added. > > >> diff --git

Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller

2019-03-28 Thread James Morse
Hi Rob, Yash, On 28/03/2019 13:16, Rob Herring wrote: > On Tue, Mar 12, 2019 at 02:51:00PM +0530, Yash Shah wrote: >> DT documentation for L2 cache controller added. >> diff --git a/Documentation/devicetree/bindings/edac/sifive-edac-l2.txt >>

Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller

2019-03-28 Thread Rob Herring
On Tue, Mar 12, 2019 at 02:51:00PM +0530, Yash Shah wrote: > DT documentation for L2 cache controller added. > > Signed-off-by: Yash Shah > --- > .../devicetree/bindings/edac/sifive-edac-l2.txt| 31 > ++ > 1 file changed, 31 insertions(+) > create mode 100644

[PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller

2019-03-12 Thread Yash Shah
DT documentation for L2 cache controller added. Signed-off-by: Yash Shah --- .../devicetree/bindings/edac/sifive-edac-l2.txt| 31 ++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/sifive-edac-l2.txt diff --git