On Sun, Mar 8, 2015 at 12:50 PM, Guenter Roeck wrote:
> On 03/08/2015 12:30 PM, Andy Lutomirski wrote:
> [ ... ]
>
>>>
One other question: from my reading of the spec, it should be possible
to
augment this driver to expose a temporate sensor subdevice that shows
recent cached
On 03/08/2015 12:30 PM, Andy Lutomirski wrote:
[ ... ]
One other question: from my reading of the spec, it should be possible to
augment this driver to expose a temporate sensor subdevice that shows
recent cached temperatures from HW DIMM measurements. They would be
redundant with the jc42
On Sun, Mar 8, 2015 at 8:39 AM, Guenter Roeck wrote:
> On 03/08/2015 07:03 AM, Andy Lutomirski wrote:
>>
>> On Mar 7, 2015 6:39 AM, "Guenter Roeck" wrote:
>>>
>>>
>>> On 03/06/2015 06:50 PM, Andy Lutomirski wrote:
Sandy Bridge Xeon and Extreme chips have integrated memory
On 03/08/2015 07:03 AM, Andy Lutomirski wrote:
On Mar 7, 2015 6:39 AM, "Guenter Roeck" wrote:
On 03/06/2015 06:50 PM, Andy Lutomirski wrote:
Sandy Bridge Xeon and Extreme chips have integrated memory
controllers with (rather limited) onboard SMBUS masters. This
driver gives access to the
On Mar 7, 2015 6:39 AM, "Guenter Roeck" wrote:
>
> On 03/06/2015 06:50 PM, Andy Lutomirski wrote:
>>
>> Sandy Bridge Xeon and Extreme chips have integrated memory
>> controllers with (rather limited) onboard SMBUS masters. This
>> driver gives access to the bus.
>>
>> There are various groups
On 03/08/2015 12:30 PM, Andy Lutomirski wrote:
[ ... ]
One other question: from my reading of the spec, it should be possible to
augment this driver to expose a temporate sensor subdevice that shows
recent cached temperatures from HW DIMM measurements. They would be
redundant with the jc42
On Sun, Mar 8, 2015 at 8:39 AM, Guenter Roeck li...@roeck-us.net wrote:
On 03/08/2015 07:03 AM, Andy Lutomirski wrote:
On Mar 7, 2015 6:39 AM, Guenter Roeck li...@roeck-us.net wrote:
On 03/06/2015 06:50 PM, Andy Lutomirski wrote:
Sandy Bridge Xeon and Extreme chips have integrated memory
On Sun, Mar 8, 2015 at 12:50 PM, Guenter Roeck li...@roeck-us.net wrote:
On 03/08/2015 12:30 PM, Andy Lutomirski wrote:
[ ... ]
One other question: from my reading of the spec, it should be possible
to
augment this driver to expose a temporate sensor subdevice that shows
recent cached
On Mar 7, 2015 6:39 AM, Guenter Roeck li...@roeck-us.net wrote:
On 03/06/2015 06:50 PM, Andy Lutomirski wrote:
Sandy Bridge Xeon and Extreme chips have integrated memory
controllers with (rather limited) onboard SMBUS masters. This
driver gives access to the bus.
There are various groups
On 03/08/2015 07:03 AM, Andy Lutomirski wrote:
On Mar 7, 2015 6:39 AM, Guenter Roeck li...@roeck-us.net wrote:
On 03/06/2015 06:50 PM, Andy Lutomirski wrote:
Sandy Bridge Xeon and Extreme chips have integrated memory
controllers with (rather limited) onboard SMBUS masters. This
driver gives
On 03/06/2015 06:50 PM, Andy Lutomirski wrote:
Sandy Bridge Xeon and Extreme chips have integrated memory
controllers with (rather limited) onboard SMBUS masters. This
driver gives access to the bus.
There are various groups working on standardizing a way to arbitrate
access to the bus between
Just two nits.
Andy Lutomirski schreef op vr 06-03-2015 om 18:50 [-0800]:
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -149,6 +149,24 @@ config I2C_ISMT
> This driver can also be built as a module. If so, the module will be
> called i2c-ismt.
>
>
On 03/06/2015 06:50 PM, Andy Lutomirski wrote:
Sandy Bridge Xeon and Extreme chips have integrated memory
controllers with (rather limited) onboard SMBUS masters. This
driver gives access to the bus.
There are various groups working on standardizing a way to arbitrate
access to the bus between
Just two nits.
Andy Lutomirski schreef op vr 06-03-2015 om 18:50 [-0800]:
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -149,6 +149,24 @@ config I2C_ISMT
This driver can also be built as a module. If so, the module will be
called i2c-ismt.
+config
Sandy Bridge Xeon and Extreme chips have integrated memory
controllers with (rather limited) onboard SMBUS masters. This
driver gives access to the bus.
There are various groups working on standardizing a way to arbitrate
access to the bus between the OS, SMM firmware, a BMC, hardware
thermal
Sandy Bridge Xeon and Extreme chips have integrated memory
controllers with (rather limited) onboard SMBUS masters. This
driver gives access to the bus.
There are various groups working on standardizing a way to arbitrate
access to the bus between the OS, SMM firmware, a BMC, hardware
thermal
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