On 08-Feb-18 8:46 PM, Andy Shevchenko wrote:
> On Thu, Feb 8, 2018 at 2:55 PM, Vignesh R wrote:
>> Currently, data in RX FIFO is read based on UART_LSR register state even
>> if RDI and RLSI interrupts are disabled in UART_IER register.
>> This is because when IRQ handler is called due to TX FIF
On Thu, Feb 8, 2018 at 2:55 PM, Vignesh R wrote:
> Currently, data in RX FIFO is read based on UART_LSR register state even
> if RDI and RLSI interrupts are disabled in UART_IER register.
> This is because when IRQ handler is called due to TX FIFO empty event,
> RX FIFO is serviced based on UART_L
Currently, data in RX FIFO is read based on UART_LSR register state even
if RDI and RLSI interrupts are disabled in UART_IER register.
This is because when IRQ handler is called due to TX FIFO empty event,
RX FIFO is serviced based on UART_LSR register status instead of
UART_IIR status. This defeat
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