Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-28 Thread Maxime Ripard
On Thu, Sep 28, 2017 at 02:24:18PM +, icen...@aosc.io wrote: > 在 2017-09-28 22:20，Maxime Ripard 写道： > > On Thu, Sep 28, 2017 at 10:42:39AM +, icen...@aosc.io wrote: > > > > On Sat, Sep 23, 2017 at 12:15:29AM +, Icenowy Zheng wrote: > > > > > The A64 PLL_CPU clock has the same

Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-28 Thread Maxime Ripard
On Thu, Sep 28, 2017 at 02:24:18PM +, icen...@aosc.io wrote: > 在 2017-09-28 22:20，Maxime Ripard 写道： > > On Thu, Sep 28, 2017 at 10:42:39AM +, icen...@aosc.io wrote: > > > > On Sat, Sep 23, 2017 at 12:15:29AM +, Icenowy Zheng wrote: > > > > > The A64 PLL_CPU clock has the same

Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-28 Thread icenowy
在 2017-09-28 22:20，Maxime Ripard 写道： On Thu, Sep 28, 2017 at 10:42:39AM +, icen...@aosc.io wrote: > On Sat, Sep 23, 2017 at 12:15:29AM +, Icenowy Zheng wrote: > > The A64 PLL_CPU clock has the same instability if some factor changed > > without the PLL gated like other SoCs with

Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-28 Thread icenowy
在 2017-09-28 22:20，Maxime Ripard 写道： On Thu, Sep 28, 2017 at 10:42:39AM +, icen...@aosc.io wrote: > On Sat, Sep 23, 2017 at 12:15:29AM +, Icenowy Zheng wrote: > > The A64 PLL_CPU clock has the same instability if some factor changed > > without the PLL gated like other SoCs with

Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-28 Thread Maxime Ripard
On Thu, Sep 28, 2017 at 10:42:39AM +, icen...@aosc.io wrote: > > On Sat, Sep 23, 2017 at 12:15:29AM +, Icenowy Zheng wrote: > > > The A64 PLL_CPU clock has the same instability if some factor changed > > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, > > > H3. > >

Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-28 Thread Maxime Ripard
On Thu, Sep 28, 2017 at 10:42:39AM +, icen...@aosc.io wrote: > > On Sat, Sep 23, 2017 at 12:15:29AM +, Icenowy Zheng wrote: > > > The A64 PLL_CPU clock has the same instability if some factor changed > > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, > > > H3. > >

Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-28 Thread icenowy
在 2017-09-28 18:27，Maxime Ripard 写道： Hi, On Sat, Sep 23, 2017 at 12:15:29AM +, Icenowy Zheng wrote: The A64 PLL_CPU clock has the same instability if some factor changed without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, H3. Add the mux and pll notifiers for A64 CPU

Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-28 Thread icenowy
在 2017-09-28 18:27，Maxime Ripard 写道： Hi, On Sat, Sep 23, 2017 at 12:15:29AM +, Icenowy Zheng wrote: The A64 PLL_CPU clock has the same instability if some factor changed without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, H3. Add the mux and pll notifiers for A64 CPU

Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-28 Thread Maxime Ripard
Hi, On Sat, Sep 23, 2017 at 12:15:29AM +, Icenowy Zheng wrote: > The A64 PLL_CPU clock has the same instability if some factor changed > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, > H3. > > Add the mux and pll notifiers for A64 CPU clock to workaround the >

Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-28 Thread Maxime Ripard
Hi, On Sat, Sep 23, 2017 at 12:15:29AM +, Icenowy Zheng wrote: > The A64 PLL_CPU clock has the same instability if some factor changed > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, > H3. > > Add the mux and pll notifiers for A64 CPU clock to workaround the >

[PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-22 Thread Icenowy Zheng
The A64 PLL_CPU clock has the same instability if some factor changed without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, H3. Add the mux and pll notifiers for A64 CPU clock to workaround the problem. Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") Signed-off-by: Icenowy

[PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-22 Thread Icenowy Zheng
The A64 PLL_CPU clock has the same instability if some factor changed without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, H3. Add the mux and pll notifiers for A64 CPU clock to workaround the problem. Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") Signed-off-by: Icenowy