Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

2017-10-19 Thread Daniel Lezcano
On 19/10/2017 11:18, Thomas Gleixner wrote: > On Thu, 19 Oct 2017, Daniel Lezcano wrote: >> On 18/10/2017 22:34, Thomas Gleixner wrote: >>> On Wed, 11 Oct 2017, Matt Redfearn wrote: >>> When the MIPS GIC clockevent code was written, it appears to have inherited the 0x300 cycle min delta f

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

2017-10-19 Thread Matt Redfearn
On 19/10/17 10:09, Daniel Lezcano wrote: On 11/10/2017 16:01, Matt Redfearn wrote: When the MIPS GIC clockevent code was written, it appears to have inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This is suboptimal for two reasons. Firstly, the CPU timer counts once every

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

2017-10-19 Thread Thomas Gleixner
On Thu, 19 Oct 2017, Daniel Lezcano wrote: > On 18/10/2017 22:34, Thomas Gleixner wrote: > > On Wed, 11 Oct 2017, Matt Redfearn wrote: > > > >> When the MIPS GIC clockevent code was written, it appears to have > >> inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This > >> is su

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

2017-10-19 Thread Daniel Lezcano
On 18/10/2017 22:34, Thomas Gleixner wrote: > On Wed, 11 Oct 2017, Matt Redfearn wrote: > >> When the MIPS GIC clockevent code was written, it appears to have >> inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This >> is suboptimal for two reasons. >> >> Firstly, the CPU timer

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

2017-10-19 Thread Daniel Lezcano
On 11/10/2017 16:01, Matt Redfearn wrote: > When the MIPS GIC clockevent code was written, it appears to have > inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This > is suboptimal for two reasons. > > Firstly, the CPU timer counts once every other cycle (i.e. half the > clock

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

2017-10-19 Thread Thomas Gleixner
On Thu, 19 Oct 2017, Matt Redfearn wrote: > On 18/10/17 21:34, Thomas Gleixner wrote: > > On Wed, 11 Oct 2017, Matt Redfearn wrote: > > > Secondly, the fixed min delta ignores the fact that with MIPS > > > multithreading active, execution resource within a core is shared > > > between the hardware

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

2017-10-19 Thread Matt Redfearn
On 18/10/17 21:34, Thomas Gleixner wrote: On Wed, 11 Oct 2017, Matt Redfearn wrote: When the MIPS GIC clockevent code was written, it appears to have inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This is suboptimal for two reasons. Firstly, the CPU timer counts once ever

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

2017-10-18 Thread Thomas Gleixner
On Wed, 11 Oct 2017, Matt Redfearn wrote: > When the MIPS GIC clockevent code was written, it appears to have > inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This > is suboptimal for two reasons. > > Firstly, the CPU timer counts once every other cycle (i.e. half the > clock

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

2017-10-17 Thread Daniel Lezcano
On 11/10/2017 16:01, Matt Redfearn wrote: > When the MIPS GIC clockevent code was written, it appears to have > inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This > is suboptimal for two reasons. > > Firstly, the CPU timer counts once every other cycle (i.e. half the > clock

[PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

2017-10-11 Thread Matt Redfearn
When the MIPS GIC clockevent code was written, it appears to have inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This is suboptimal for two reasons. Firstly, the CPU timer counts once every other cycle (i.e. half the clock rate). The GIC counts once per clock. Assuming that th