Re: [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

2017-04-05 Thread Chen-Yu Tsai
On Wed, Apr 5, 2017 at 8:58 PM, Kishon Vijay Abraham I wrote: > > > On Wednesday 05 April 2017 06:20 PM, Icenowy Zheng wrote: >> From: Icenowy Zheng >> >> Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two >> controllers: one is MUSB and the

Re: [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

2017-04-05 Thread Chen-Yu Tsai
On Wed, Apr 5, 2017 at 8:58 PM, Kishon Vijay Abraham I wrote: > > > On Wednesday 05 April 2017 06:20 PM, Icenowy Zheng wrote: >> From: Icenowy Zheng >> >> Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two >> controllers: one is MUSB and the other is a EHCI/OHCI pair. >> >>

Re: [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

2017-04-05 Thread Kishon Vijay Abraham I
On Wednesday 05 April 2017 06:20 PM, Icenowy Zheng wrote: > From: Icenowy Zheng > > Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two > controllers: one is MUSB and the other is a EHCI/OHCI pair. > > When it's routed to EHCI/OHCI pair, it will needs a

Re: [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

2017-04-05 Thread Kishon Vijay Abraham I
On Wednesday 05 April 2017 06:20 PM, Icenowy Zheng wrote: > From: Icenowy Zheng > > Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two > controllers: one is MUSB and the other is a EHCI/OHCI pair. > > When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to >

[PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

2017-04-05 Thread Icenowy Zheng
From: Icenowy Zheng Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two controllers: one is MUSB and the other is a EHCI/OHCI pair. When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to tweak, like other EHCI/OHCI pairs in Allwinner SoCs. Add

[PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

2017-04-05 Thread Icenowy Zheng
From: Icenowy Zheng Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two controllers: one is MUSB and the other is a EHCI/OHCI pair. When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to tweak, like other EHCI/OHCI pairs in Allwinner SoCs. Add this to the