Re: [PATCH 1/3] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.

2015-05-22 Thread Michal Simek
On 05/22/2015 01:37 AM, Moritz Fischer wrote: > The Xilinx LogiCORE IP mailbox is a FPGA core that allows for > interprocessor communication via AXI4 memory mapped / AXI4 stream > interfaces. > > It is single channel per core and allows for transmit and receive. > > Signed-off-by: Moritz Fischer

Re: [PATCH 1/3] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.

2015-05-21 Thread Shubhrajyoti Datta
Hi Moritz, Overall looks good some nitpicks below. On Fri, May 22, 2015 at 5:07 AM, Moritz Fischer wrote: > The Xilinx LogiCORE IP mailbox is a FPGA core that allows for > interprocessor communication via AXI4 memory mapped / AXI4 stream > interfaces. > > It is single channel per core and allow

[PATCH 1/3] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.

2015-05-21 Thread Moritz Fischer
The Xilinx LogiCORE IP mailbox is a FPGA core that allows for interprocessor communication via AXI4 memory mapped / AXI4 stream interfaces. It is single channel per core and allows for transmit and receive. Signed-off-by: Moritz Fischer --- drivers/mailbox/Kconfig | 8 + drivers/mail