Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

2017-03-24 Thread Peter Zijlstra
On Fri, Mar 24, 2017 at 02:15:16PM +, Liang, Kan wrote: > > > > On Thu, 23 Mar 2017, Peter Zijlstra wrote: > > > On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.li...@intel.com wrote: > > > > + for_each_possible_cpu(cpu) { > > > > + rdmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, >

RE: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

2017-03-24 Thread Liang, Kan
> On Thu, 23 Mar 2017, Peter Zijlstra wrote: > > On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.li...@intel.com wrote: > > > + for_each_possible_cpu(cpu) { > > > + rdmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, > &debugctlmsr); > > > + if (val) > > > + wrmsrl_on_cpu(cpu,

Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

2017-03-24 Thread Thomas Gleixner
On Thu, 23 Mar 2017, Peter Zijlstra wrote: > On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.li...@intel.com wrote: > > + for_each_possible_cpu(cpu) { > > + rdmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, &debugctlmsr); > > + if (val) > > + wrmsrl_on_cpu(cpu, MSR_IA32

Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

2017-03-24 Thread Peter Zijlstra
On Thu, Mar 23, 2017 at 03:23:03PM -0700, Andi Kleen wrote: > On Thu, Mar 23, 2017 at 09:31:38PM +0100, Peter Zijlstra wrote: > > On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.li...@intel.com wrote: > > > From: Kan Liang > > > > > > When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performa

Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

2017-03-23 Thread Andi Kleen
On Thu, Mar 23, 2017 at 09:31:38PM +0100, Peter Zijlstra wrote: > On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.li...@intel.com wrote: > > From: Kan Liang > > > > When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance > > counters will be effected. There is no way to do per-counter f

RE: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

2017-03-23 Thread Liang, Kan
> On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.li...@intel.com wrote: > > From: Kan Liang > > > > When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all > performance > > counters will be effected. There is no way to do per-counter freeze on > > smi. So it should not use the per-event interface

Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

2017-03-23 Thread Peter Zijlstra
On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.li...@intel.com wrote: > + for_each_possible_cpu(cpu) { > + rdmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, &debugctlmsr); > + if (val) > + wrmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, debugctlmsr | > DEBUGCTLMSR_FR

Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

2017-03-23 Thread Peter Zijlstra
On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.li...@intel.com wrote: > From: Kan Liang > > When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance > counters will be effected. There is no way to do per-counter freeze > on smi. So it should not use the per-event interface (e.g. ioctl o

[PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

2017-03-23 Thread kan . liang
From: Kan Liang When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance counters will be effected. There is no way to do per-counter freeze on smi. So it should not use the per-event interface (e.g. ioctl or event attribute) to set FREEZE_WHILE_SMM bit. Adds sysfs entry /sys/device/c