On 04/03/21 12:51 am, Grygorii Strashko wrote:
> From: Vignesh Raghavendra
>
> Add CPSW3g DT node with two external ports, MDIO and CPTS support. For
> CPSW3g DMA channels the ASEL is set to 15 (AM642x per DMA channel coherency
> feature), so that CPSW DMA channel participates in Coherency
From: Vignesh Raghavendra
Add CPSW3g DT node with two external ports, MDIO and CPTS support. For
CPSW3g DMA channels the ASEL is set to 15 (AM642x per DMA channel coherency
feature), so that CPSW DMA channel participates in Coherency and thus avoid
need to cache maintenance for SKBs. This
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