On Tuesday 31 July 2012, Chao Xie wrote:
> +static int clk_apbc_prepare(struct clk_hw *hw)
> +{
> + struct clk_apbc *apbc = to_clk_apbc(hw);
> + unsigned int data;
> + unsigned long flags = 0;
> +
> + /*
> + * It may share same register as MUX clock,
> + * and it will
From: Chao Xie
add mmp specific clocks including apbc cloks, apmu clocks,
and pll2, fraction clocks
Signed-off-by: Chao Xie
---
drivers/clk/Makefile |3 +
drivers/clk/mmp/Makefile |5 ++
drivers/clk/mmp/clk-apbc.c | 141 +++
From: Chao Xie chao@marvell.com
add mmp specific clocks including apbc cloks, apmu clocks,
and pll2, fraction clocks
Signed-off-by: Chao Xie xiechao.m...@gmail.com
---
drivers/clk/Makefile |3 +
drivers/clk/mmp/Makefile |5 ++
drivers/clk/mmp/clk-apbc.c | 141
On Tuesday 31 July 2012, Chao Xie wrote:
+static int clk_apbc_prepare(struct clk_hw *hw)
+{
+ struct clk_apbc *apbc = to_clk_apbc(hw);
+ unsigned int data;
+ unsigned long flags = 0;
+
+ /*
+ * It may share same register as MUX clock,
+ * and it will impact FNCLK
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