Re: [PATCH 1/5] riscv: Coding convention for xchg

2020-11-25 Thread Guo Ren
On Tue, Nov 24, 2020 at 10:29 PM Peter Zijlstra wrote: > > On Tue, Nov 24, 2020 at 01:43:53PM +, guo...@kernel.org wrote: > > From: Guo Ren > > > > This is prepare for QUEUED_SPINLOCKS which need xchg support short > > type value. > > - Remove unused codes (xchg32, xchg64, cmpxchg32 ...) >

Re: [PATCH 1/5] riscv: Coding convention for xchg

2020-11-24 Thread Peter Zijlstra
On Tue, Nov 24, 2020 at 01:43:53PM +, guo...@kernel.org wrote: > From: Guo Ren > > This is prepare for QUEUED_SPINLOCKS which need xchg support short > type value. > - Remove unused codes (xchg32, xchg64, cmpxchg32 ...) > - Combine xchg_relaxed, xchg_acquire, xchg_release into one asm > -

[PATCH 1/5] riscv: Coding convention for xchg

2020-11-24 Thread guoren
From: Guo Ren This is prepare for QUEUED_SPINLOCKS which need xchg support short type value. - Remove unused codes (xchg32, xchg64, cmpxchg32 ...) - Combine xchg_relaxed, xchg_acquire, xchg_release into one asm - Make atomic.aq/rl with seperated fence acquire & release Signed-off-by: Guo Ren