Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, Sep 12, 2014 at 01:03:12PM -0700, Andy Lutomirski wrote: > On Fri, Sep 12, 2014 at 12:25 PM, Konrad Rzeszutek Wilk > wrote: > > On Thu, Sep 04, 2014 at 04:34:43PM -0700, Andy Lutomirski wrote: > >> At the very least, anyone who plugs an NV-DIMM into a 32-bit machine > >> is nuts, and not

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, Sep 12, 2014 at 12:25 PM, Konrad Rzeszutek Wilk wrote: > On Thu, Sep 04, 2014 at 04:34:43PM -0700, Andy Lutomirski wrote: >> At the very least, anyone who plugs an NV-DIMM into a 32-bit machine >> is nuts, and not just because I'd be somewhat amazed if it even >> physically fits into the

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, Sep 04, 2014 at 04:34:43PM -0700, Andy Lutomirski wrote: > On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh > wrote: > > On Thu, 04 Sep 2014, H. Peter Anvin wrote: > >> On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote: > >> > I am worried of uncharted territory, here.

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, Sep 04, 2014 at 04:34:43PM -0700, Andy Lutomirski wrote: On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh h...@hmh.eng.br wrote: On Thu, 04 Sep 2014, H. Peter Anvin wrote: On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote: I am worried of uncharted territory,

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, Sep 12, 2014 at 12:25 PM, Konrad Rzeszutek Wilk konrad.w...@oracle.com wrote: On Thu, Sep 04, 2014 at 04:34:43PM -0700, Andy Lutomirski wrote: At the very least, anyone who plugs an NV-DIMM into a 32-bit machine is nuts, and not just because I'd be somewhat amazed if it even physically

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, Sep 12, 2014 at 01:03:12PM -0700, Andy Lutomirski wrote: On Fri, Sep 12, 2014 at 12:25 PM, Konrad Rzeszutek Wilk konrad.w...@oracle.com wrote: On Thu, Sep 04, 2014 at 04:34:43PM -0700, Andy Lutomirski wrote: At the very least, anyone who plugs an NV-DIMM into a 32-bit machine is

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, 05 Sep 2014, Toshi Kani wrote: > On Fri, 2014-09-05 at 12:23 +0200, Ingo Molnar wrote: > > Any reason why we have to create such a sharp boundary, instead > > of simply saying: 'disable PAT on all x86 CPU families that have > > at least one buggy model'? > > > > That would nicely sort

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, 05 Sep 2014, Toshi Kani wrote: On Fri, 2014-09-05 at 12:23 +0200, Ingo Molnar wrote: Any reason why we have to create such a sharp boundary, instead of simply saying: 'disable PAT on all x86 CPU families that have at least one buggy model'? That would nicely sort out all the

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, 2014-09-05 at 08:41 -0700, H. Peter Anvin wrote: > On 09/05/2014 08:22 AM, Toshi Kani wrote: > > On Fri, 2014-09-05 at 08:07 -0700, H. Peter Anvin wrote: > >> On 09/05/2014 07:00 AM, Toshi Kani wrote: > >>> > >>> That's a fine idea, but as Ingo also suggested, I am going to disable > >>>

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On 09/05/2014 08:22 AM, Toshi Kani wrote: > On Fri, 2014-09-05 at 08:07 -0700, H. Peter Anvin wrote: >> On 09/05/2014 07:00 AM, Toshi Kani wrote: >>> >>> That's a fine idea, but as Ingo also suggested, I am going to disable >>> this feature on all Pentium 4 models. That should give us a safety

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, 2014-09-05 at 08:07 -0700, H. Peter Anvin wrote: > On 09/05/2014 07:00 AM, Toshi Kani wrote: > > > > That's a fine idea, but as Ingo also suggested, I am going to disable > > this feature on all Pentium 4 models. That should give us a safety > > margin. Using slot 4 has a benefit that

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On 09/05/2014 07:00 AM, Toshi Kani wrote: > > That's a fine idea, but as Ingo also suggested, I am going to disable > this feature on all Pentium 4 models. That should give us a safety > margin. Using slot 4 has a benefit that it keeps the PAT setup > consistent with Xen. > Slot 4 is

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 2014-09-04 at 17:51 -0700, Andy Lutomirski wrote: > On Thu, Sep 4, 2014 at 5:29 PM, Toshi Kani wrote: > > On Thu, 2014-09-04 at 16:34 -0700, Andy Lutomirski wrote: > >> On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh > >> wrote: > >> > On Thu, 04 Sep 2014, H. Peter Anvin

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, 2014-09-05 at 12:23 +0200, Ingo Molnar wrote: > * Toshi Kani wrote: > > > On Thu, 2014-09-04 at 14:31 -0600, Toshi Kani wrote: > > > On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote: > > > > On Thu, 04 Sep 2014, Toshi Kani wrote: > > > > > This patch sets WT to the

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

* Toshi Kani wrote: > On Thu, 2014-09-04 at 14:31 -0600, Toshi Kani wrote: > > On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote: > > > On Thu, 04 Sep 2014, Toshi Kani wrote: > > > > This patch sets WT to the PA4 slot in the PAT MSR when the processor > > > > is not affected

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

* Toshi Kani toshi.k...@hp.com wrote: On Thu, 2014-09-04 at 14:31 -0600, Toshi Kani wrote: On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote: On Thu, 04 Sep 2014, Toshi Kani wrote: This patch sets WT to the PA4 slot in the PAT MSR when the processor is not

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, 2014-09-05 at 12:23 +0200, Ingo Molnar wrote: * Toshi Kani toshi.k...@hp.com wrote: On Thu, 2014-09-04 at 14:31 -0600, Toshi Kani wrote: On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote: On Thu, 04 Sep 2014, Toshi Kani wrote: This patch sets WT to the

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 2014-09-04 at 17:51 -0700, Andy Lutomirski wrote: On Thu, Sep 4, 2014 at 5:29 PM, Toshi Kani toshi.k...@hp.com wrote: On Thu, 2014-09-04 at 16:34 -0700, Andy Lutomirski wrote: On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh h...@hmh.eng.br wrote: On Thu, 04 Sep 2014,

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On 09/05/2014 07:00 AM, Toshi Kani wrote: That's a fine idea, but as Ingo also suggested, I am going to disable this feature on all Pentium 4 models. That should give us a safety margin. Using slot 4 has a benefit that it keeps the PAT setup consistent with Xen. Slot 4 is also the

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, 2014-09-05 at 08:07 -0700, H. Peter Anvin wrote: On 09/05/2014 07:00 AM, Toshi Kani wrote: That's a fine idea, but as Ingo also suggested, I am going to disable this feature on all Pentium 4 models. That should give us a safety margin. Using slot 4 has a benefit that it keeps

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On 09/05/2014 08:22 AM, Toshi Kani wrote: On Fri, 2014-09-05 at 08:07 -0700, H. Peter Anvin wrote: On 09/05/2014 07:00 AM, Toshi Kani wrote: That's a fine idea, but as Ingo also suggested, I am going to disable this feature on all Pentium 4 models. That should give us a safety margin.

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Fri, 2014-09-05 at 08:41 -0700, H. Peter Anvin wrote: On 09/05/2014 08:22 AM, Toshi Kani wrote: On Fri, 2014-09-05 at 08:07 -0700, H. Peter Anvin wrote: On 09/05/2014 07:00 AM, Toshi Kani wrote: That's a fine idea, but as Ingo also suggested, I am going to disable this feature on all

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, Sep 4, 2014 at 5:29 PM, Toshi Kani wrote: > On Thu, 2014-09-04 at 16:34 -0700, Andy Lutomirski wrote: >> On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh >> wrote: >> > On Thu, 04 Sep 2014, H. Peter Anvin wrote: >> >> On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote:

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 2014-09-04 at 16:34 -0700, Andy Lutomirski wrote: > On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh > wrote: > > On Thu, 04 Sep 2014, H. Peter Anvin wrote: > >> On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote: > >> > I am worried of uncharted territory, here. I'd

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 2014-09-04 at 14:31 -0600, Toshi Kani wrote: > On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote: > > On Thu, 04 Sep 2014, Toshi Kani wrote: > > > This patch sets WT to the PA4 slot in the PAT MSR when the processor > > > is not affected by the PAT errata. The upper 4

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh wrote: > On Thu, 04 Sep 2014, H. Peter Anvin wrote: >> On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote: >> > I am worried of uncharted territory, here. I'd actually advocate for not >> > enabling the upper four PAT entries on

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 04 Sep 2014, H. Peter Anvin wrote: > On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote: > > I am worried of uncharted territory, here. I'd actually advocate for not > > enabling the upper four PAT entries on IA-32 at all, unless Windows 9X / XP > > is using them as well. Is this

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, Sep 4, 2014 at 1:31 PM, Toshi Kani wrote: > On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote: >> On Thu, 04 Sep 2014, Toshi Kani wrote: >> > This patch sets WT to the PA4 slot in the PAT MSR when the processor >> > is not affected by the PAT errata. The upper 4 slots

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote: > On Thu, 04 Sep 2014, Toshi Kani wrote: > > This patch sets WT to the PA4 slot in the PAT MSR when the processor > > is not affected by the PAT errata. The upper 4 slots of the PAT MSR > > are continued to be unused on the

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote: > > I am worried of uncharted territory, here. I'd actually advocate for not > enabling the upper four PAT entries on IA-32 at all, unless Windows 9X / XP > is using them as well. Is this a real concern, or am I being overly > cautious?

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 04 Sep 2014, Toshi Kani wrote: > This patch sets WT to the PA4 slot in the PAT MSR when the processor > is not affected by the PAT errata. The upper 4 slots of the PAT MSR > are continued to be unused on the following Intel processors. > > errata cpuid >

[PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

This patch sets WT to the PA4 slot in the PAT MSR when the processor is not affected by the PAT errata. The upper 4 slots of the PAT MSR are continued to be unused on the following Intel processors. errata cpuid -- Pentium 2, A52 family 0x6,

[PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

This patch sets WT to the PA4 slot in the PAT MSR when the processor is not affected by the PAT errata. The upper 4 slots of the PAT MSR are continued to be unused on the following Intel processors. errata cpuid -- Pentium 2, A52 family 0x6,

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 04 Sep 2014, Toshi Kani wrote: This patch sets WT to the PA4 slot in the PAT MSR when the processor is not affected by the PAT errata. The upper 4 slots of the PAT MSR are continued to be unused on the following Intel processors. errata cpuid

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote: I am worried of uncharted territory, here. I'd actually advocate for not enabling the upper four PAT entries on IA-32 at all, unless Windows 9X / XP is using them as well. Is this a real concern, or am I being overly cautious?

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote: On Thu, 04 Sep 2014, Toshi Kani wrote: This patch sets WT to the PA4 slot in the PAT MSR when the processor is not affected by the PAT errata. The upper 4 slots of the PAT MSR are continued to be unused on the following

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, Sep 4, 2014 at 1:31 PM, Toshi Kani toshi.k...@hp.com wrote: On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote: On Thu, 04 Sep 2014, Toshi Kani wrote: This patch sets WT to the PA4 slot in the PAT MSR when the processor is not affected by the PAT errata. The upper

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 04 Sep 2014, H. Peter Anvin wrote: On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote: I am worried of uncharted territory, here. I'd actually advocate for not enabling the upper four PAT entries on IA-32 at all, unless Windows 9X / XP is using them as well. Is this a real

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh h...@hmh.eng.br wrote: On Thu, 04 Sep 2014, H. Peter Anvin wrote: On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote: I am worried of uncharted territory, here. I'd actually advocate for not enabling the upper four PAT

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 2014-09-04 at 14:31 -0600, Toshi Kani wrote: On Thu, 2014-09-04 at 17:11 -0300, Henrique de Moraes Holschuh wrote: On Thu, 04 Sep 2014, Toshi Kani wrote: This patch sets WT to the PA4 slot in the PAT MSR when the processor is not affected by the PAT errata. The upper 4 slots of

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, 2014-09-04 at 16:34 -0700, Andy Lutomirski wrote: On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh h...@hmh.eng.br wrote: On Thu, 04 Sep 2014, H. Peter Anvin wrote: On 09/04/2014 01:11 PM, Henrique de Moraes Holschuh wrote: I am worried of uncharted territory, here.

Re: [PATCH 1/5] x86, mm, pat: Set WT to PA4 slot of PAT MSR

On Thu, Sep 4, 2014 at 5:29 PM, Toshi Kani toshi.k...@hp.com wrote: On Thu, 2014-09-04 at 16:34 -0700, Andy Lutomirski wrote: On Thu, Sep 4, 2014 at 4:19 PM, Henrique de Moraes Holschuh h...@hmh.eng.br wrote: On Thu, 04 Sep 2014, H. Peter Anvin wrote: On 09/04/2014 01:11 PM, Henrique de