Re: [PATCH 1/6] dmaengine: xilinx_dma: fix splitting transfer causes misalignments

2018-06-20 Thread Andrea Merello
.org; dan.j.willi...@intel.com; Michal Simek >> ; Appana Durga Kedareswara Rao >> ; dmaeng...@vger.kernel.org >> Cc: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org; >> Andrea Merello >> Subject: [PATCH 1/6] dmaengine: xilinx_dma: fix splitting tr

RE: [PATCH 1/6] dmaengine: xilinx_dma: fix splitting transfer causes misalignments

2018-06-20 Thread Radhey Shyam Pandey
ara Rao > ; dmaeng...@vger.kernel.org > Cc: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org; > Andrea Merello > Subject: [PATCH 1/6] dmaengine: xilinx_dma: fix splitting transfer causes > misalignments We should rephrase commit message to something like "In axidma s

[PATCH 1/6] dmaengine: xilinx_dma: fix splitting transfer causes misalignments

2018-06-20 Thread Andrea Merello
Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length. This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW. This patch eventually ad