Reviewed-by: Mikko Perttunen
On 02/22/2017 05:13 PM, Peter De Schrijver wrote:
pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather
than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add pll_a1
to the set of clocks defined for Tegra210.
Reviewed-by: Mikko Perttunen
On 02/22/2017 05:13 PM, Peter De Schrijver wrote:
pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather
than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add pll_a1
to the set of clocks defined for Tegra210.
Signed-off-by: Peter De
pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather
than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add pll_a1
to the set of clocks defined for Tegra210.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-tegra210.c | 3 ++-
pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather
than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add pll_a1
to the set of clocks defined for Tegra210.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-tegra210.c | 3 ++-
1 file changed, 2
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