Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface

2017-01-24 Thread Shivappa Vikas
On Mon, 23 Jan 2017, Thomas Gleixner wrote: On Mon, 23 Jan 2017, Shivappa Vikas wrote: On Wed, 18 Jan 2017, Thomas Gleixner wrote: If it's going to stay, then Intel should be able to provide simple tables which give us the required information for a particular CPU model. By sample table -

Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface

2017-01-23 Thread Thomas Gleixner
On Mon, 23 Jan 2017, Shivappa Vikas wrote: > On Wed, 18 Jan 2017, Thomas Gleixner wrote: > > If it's going to stay, then Intel should be able to provide simple tables > > which give us the required information for a particular CPU model. > > By sample table - does this mean we can map a throttle v

Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface

2017-01-23 Thread Shivappa Vikas
On Wed, 18 Jan 2017, Thomas Gleixner wrote: On Tue, 17 Jan 2017, Shivappa Vikas wrote: On Mon, 16 Jan 2017, Thomas Gleixner wrote: This interface is really crap. The natural way to express it is: Requested Bandwidth = X % I wanted to do it this way which did seem more intuitive but th

Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface

2017-01-18 Thread Thomas Gleixner
On Tue, 17 Jan 2017, Shivappa Vikas wrote: > On Mon, 16 Jan 2017, Thomas Gleixner wrote: > > This interface is really crap. The natural way to express it is: > > > > Requested Bandwidth = X % > > I wanted to do it this way which did seem more intuitive but the issue is with > the non-linear s

Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface

2017-01-17 Thread Shivappa Vikas
On Mon, 16 Jan 2017, Thomas Gleixner wrote: On Tue, 10 Jan 2017, Vikas Shivappa wrote: Memory b/w allocation is part of Intel RDT(resource director technology) which lets user control the amount of memory b/w (L2 external b/w) per thread. This is done programming MSR interfaces like cache al

Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface

2017-01-16 Thread Thomas Gleixner
On Tue, 10 Jan 2017, Vikas Shivappa wrote: > Memory b/w allocation is part of Intel RDT(resource director technology) > which lets user control the amount of memory b/w (L2 external b/w) per > thread. This is done programming MSR interfaces like cache allocation > technology and other RDT features

[PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface

2017-01-10 Thread Vikas Shivappa
Memory b/w allocation is part of Intel RDT(resource director technology) which lets user control the amount of memory b/w (L2 external b/w) per thread. This is done programming MSR interfaces like cache allocation technology and other RDT features. This patch adds documentation for Memory b/w alloc