3.5.7.6 -stable review patch. If anyone has any objections, please let me know.
------------------
From: Christopher Staite <ch...@yourdreamnet.co.uk>
commit bb588820ef421c6098dca1fec29c3b347f1c8c19 upstream.
Force the crtc mem requests on/off immediately rather
than waiting for the double buffered updates to kick in.
Seems we miss the update in certain conditions. Also
handle the DCE6 case.
Signed-off-by: Christopher Staite <ch...@yourdreamnet.co.uk>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Herton Ronaldo Krzesinski <herton.krzesin...@canonical.com>
---
drivers/gpu/drm/radeon/evergreen.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 2aa7fdb..c490d16 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1147,14 +1147,18 @@ void evergreen_mc_stop(struct radeon_device *rdev,
struct evergreen_mc_save *sav
if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
radeon_wait_for_vblank(rdev, i);
tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
crtc_offsets[i], 1);
WREG32(EVERGREEN_CRTC_BLANK_CONTROL +
crtc_offsets[i], tmp);
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
crtc_offsets[i], 0);
}
} else {
tmp = RREG32(EVERGREEN_CRTC_CONTROL +
crtc_offsets[i]);
if (!(tmp &
EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
radeon_wait_for_vblank(rdev, i);
tmp |=
EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
crtc_offsets[i], 1);
WREG32(EVERGREEN_CRTC_CONTROL +
crtc_offsets[i], tmp);
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
crtc_offsets[i], 0);
}
}
/* wait for the next frame */
@@ -1212,11 +1216,15 @@ void evergreen_mc_resume(struct radeon_device *rdev,
struct evergreen_mc_save *s
if (ASIC_IS_DCE6(rdev)) {
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL +
crtc_offsets[i]);
tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
crtc_offsets[i], 1);
WREG32(EVERGREEN_CRTC_BLANK_CONTROL +
crtc_offsets[i], tmp);
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
crtc_offsets[i], 0);
} else {
tmp = RREG32(EVERGREEN_CRTC_CONTROL +
crtc_offsets[i]);
tmp &=
~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
crtc_offsets[i], 1);
WREG32(EVERGREEN_CRTC_CONTROL +
crtc_offsets[i], tmp);
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK +
crtc_offsets[i], 0);
}
/* wait for the next frame */
frame_count = radeon_get_vblank_counter(rdev, i);
--
1.7.9.5
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