Re: [PATCH 13/15] riscv: clear the instruction cache and all registers when booting

On Wed, Aug 14, 2019 at 09:00:14AM +0800, Alan Kao wrote: > But it doesn't really mean that the running system has an FPU given CONFIG_FPU > enabled. Normally the existence of an FPU is checked in riscv_fill_hwcap by > searching device tree, where the code looks like > > > bool has_fpu = false;

Re: [PATCH 13/15] riscv: clear the instruction cache and all registers when booting

Hi Christoph, On Tue, Aug 13, 2019 at 05:47:45PM +0200, Christoph Hellwig wrote: > When we get booted we want a clear slate without any leaks from previous > supervisors or the firmware. Flush the instruction cache and then clear > all registers to known good values. This is really important for

Re: [PATCH 13/15] riscv: clear the instruction cache and all registers when booting

Please ignore the previous mail, I must have missed this part of the patch, > > > + csrrt0, CSR_MISA > > + andit0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D) > > + bnezt0, .Lreset_regs_done > > + In S-mode we were not able to obtain the ISA information in misa, but now the

[PATCH 13/15] riscv: clear the instruction cache and all registers when booting

When we get booted we want a clear slate without any leaks from previous supervisors or the firmware. Flush the instruction cache and then clear all registers to known good values. This is really important for the upcoming nommu support that runs on M-mode, but can't really harm when running in S