Hi Dan,
On Tue, Jun 27, 2017 at 12:07:20AM +, Daniel Lustig wrote:
> > > https://github.com/riscv/riscv-isa-manual/releases/download/riscv-user
> > > -2.2/riscv-spec-v2.2.pdf
> >
> > That's the most up to date spec.
>
> Yes, that's the most up to date public spec. Internally, the RISC-V mem
> > https://github.com/riscv/riscv-isa-manual/releases/download/riscv-user
> > -2.2/riscv-spec-v2.2.pdf
>
> That's the most up to date spec.
Yes, that's the most up to date public spec. Internally, the RISC-V memory
model task group has been working on fixing the memory model spec for the
past c
On Wed, 07 Jun 2017 06:16:11 PDT (-0700), will.dea...@arm.com wrote:
> [sorry, jumping in here because it's the only mail I have relating to
> patch 13]
>
> On Wed, Jun 07, 2017 at 02:58:50PM +0200, Peter Zijlstra wrote:
>> On Wed, Jun 07, 2017 at 02:36:27PM +0200, Peter Zijlstra wrote:
>> > Which
On Wed, 07 Jun 2017 05:58:50 PDT (-0700), pet...@infradead.org wrote:
> On Wed, Jun 07, 2017 at 02:36:27PM +0200, Peter Zijlstra wrote:
>> Which (pending the sub confusion) will generate the entire set of:
>>
>> atomic_add, atomic_add_return{_relaxed,_acquire,_release,}
>> atomic_fetch_add{_relax
On Wed, 07 Jun 2017 06:17:27 PDT (-0700), pet...@infradead.org wrote:
> On Tue, Jun 06, 2017 at 04:00:03PM -0700, Palmer Dabbelt wrote:
>> diff --git a/arch/riscv/include/asm/spinlock.h
>> b/arch/riscv/include/asm/spinlock.h
>> new file mode 100644
>> index ..9736f5714e54
>> --- /dev/n
On Sat, 2017-06-24 at 14:32 -0700, Palmer Dabbelt wrote:
> On Sat, 24 Jun 2017 08:42:05 PDT (-0700), b...@kernel.crashing.org wrote:
> > On Fri, 2017-06-23 at 19:01 -0700, Palmer Dabbelt wrote:
> > > > > +#define mmiowb() __asm__ __volatile__ ("fence io,io" : : :
> > > > > "memory");
> >
>
On Sat, 24 Jun 2017 08:42:05 PDT (-0700), b...@kernel.crashing.org wrote:
> On Fri, 2017-06-23 at 19:01 -0700, Palmer Dabbelt wrote:
>> > > +#define mmiowb()Â Â Â Â Â Â __asm__ __volatile__ ("fence io,io" : : :
>> > > "memory");
>
> I forgot if we already mentioned that but mmiowb is primarily in
On Fri, 2017-06-23 at 19:01 -0700, Palmer Dabbelt wrote:
> > > +#define mmiowb() __asm__ __volatile__ ("fence io,io" : : :
> > > "memory");
I forgot if we already mentioned that but mmiowb is primarily intended
to order MMIO stores vs. a subsequent spin_unlock.
I'm not sure an IO only fenc
On Wed, 07 Jun 2017 01:12:00 PDT (-0700), Arnd Bergmann wrote:
> On Wed, Jun 7, 2017 at 1:00 AM, Palmer Dabbelt wrote:
>> This patch adds the include files for the RISC-V port. These are mostly
>> based on the score port, but there are a lot of arm64-based files as
>> well.
>>
>> Signed-off-by: P
On Wed, Jun 07, 2017 at 03:17:27PM +0200, Peter Zijlstra wrote:
> > +static inline void arch_spin_unlock(arch_spinlock_t *lock)
> > +{
> > + __asm__ __volatile__ (
> > + "amoswap.w.rl x0, x0, %0"
> > + : "=A" (lock->lock)
> > + :: "memory");
> > +}
> > +
> > +static
On Wed, Jun 07, 2017 at 02:58:50PM +0200, Peter Zijlstra wrote:
> On Wed, Jun 07, 2017 at 02:36:27PM +0200, Peter Zijlstra wrote:
> > Which (pending the sub confusion) will generate the entire set of:
> >
> > atomic_add, atomic_add_return{_relaxed,_acquire,_release,}
> > atomic_fetch_add{_relaxe
On Tue, Jun 06, 2017 at 04:00:03PM -0700, Palmer Dabbelt wrote:
> diff --git a/arch/riscv/include/asm/spinlock.h
> b/arch/riscv/include/asm/spinlock.h
> new file mode 100644
> index ..9736f5714e54
> --- /dev/null
> +++ b/arch/riscv/include/asm/spinlock.h
> @@ -0,0 +1,155 @@
> +/*
> + *
[sorry, jumping in here because it's the only mail I have relating to
patch 13]
On Wed, Jun 07, 2017 at 02:58:50PM +0200, Peter Zijlstra wrote:
> On Wed, Jun 07, 2017 at 02:36:27PM +0200, Peter Zijlstra wrote:
> > Which (pending the sub confusion) will generate the entire set of:
> >
> > atomic
On Wed, Jun 07, 2017 at 02:36:27PM +0200, Peter Zijlstra wrote:
> Which (pending the sub confusion) will generate the entire set of:
>
> atomic_add, atomic_add_return{_relaxed,_acquire,_release,}
> atomic_fetch_add{_relaxed,_acquire,_release,}
> atomic_sub, atomic_sub_return{_relaxed,_acquire,_
On Tue, Jun 06, 2017 at 04:00:03PM -0700, Palmer Dabbelt wrote:
> diff --git a/arch/riscv/include/asm/cmpxchg.h
> b/arch/riscv/include/asm/cmpxchg.h
> new file mode 100644
> index ..c7ee1321ac18
> --- /dev/null
> +++ b/arch/riscv/include/asm/cmpxchg.h
> @@ -0,0 +1,124 @@
> +/*
> + * Co
On Wed, Jun 07, 2017 at 02:06:13PM +0200, Peter Zijlstra wrote:
> On Tue, Jun 06, 2017 at 04:00:03PM -0700, Palmer Dabbelt wrote:
> What pretty much all the other architectures do is something like:
>
> #define ATOMIC_OP(op, asm_op, c_op) \
> static __always_inline void a
On Wed, Jun 07, 2017 at 01:54:23PM +0200, Peter Zijlstra wrote:
> On Tue, Jun 06, 2017 at 04:00:03PM -0700, Palmer Dabbelt wrote:
> > +/* Assume that atomic operations are already serializing */
> > +#define smp_mb__before_atomic_dec()barrier()
> > +#define smp_mb__after_atomic_dec() barrie
On Wed, Jun 07, 2017 at 02:06:13PM +0200, Peter Zijlstra wrote:
> On Tue, Jun 06, 2017 at 04:00:03PM -0700, Palmer Dabbelt wrote:
> > +static inline int atomic_fetch_sub(unsigned int mask, atomic_t *v)
> > +{
> > + int out;
> > +
> > + __asm__ __volatile__ (
> > + "amosub.w %2, %1, %
On Tue, Jun 06, 2017 at 04:00:03PM -0700, Palmer Dabbelt wrote:
> + * atomic_add - add integer to atomic variable
> + * @i: integer value to add
> + * @v: pointer of type atomic_t
> + *
> + * Atomically adds @i to @v.
> + */
> +static inline void atomic_add(int i, atomic_t *v)
> +{
> + __asm__
On Tue, Jun 06, 2017 at 04:00:03PM -0700, Palmer Dabbelt wrote:
> +/* Assume that atomic operations are already serializing */
> +#define smp_mb__before_atomic_dec() barrier()
> +#define smp_mb__after_atomic_dec() barrier()
> +#define smp_mb__before_atomic_inc() barrier()
> +#define smp_mb__aft
On Wed, Jun 7, 2017 at 1:00 AM, Palmer Dabbelt wrote:
> This patch adds the include files for the RISC-V port. These are mostly
> based on the score port, but there are a lot of arm64-based files as
> well.
>
> Signed-off-by: Palmer Dabbelt
It might be better to split this up into several parts
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