Re: [PATCH 17/17] coresight perf: Add ETR backend support for etm-perf

2017-11-07 Thread Mathieu Poirier
On 7 November 2017 at 08:17, Mike Leach wrote: > Hi Suzuki, Mathieu, > > A follow up on Dragonboard issues... > > = > Using Suzukis debug code and some of my own home spun updates I've > got the following logging out of a typical ETR-SG session from the > DB410. > Session initiated using comm

Re: [PATCH 17/17] coresight perf: Add ETR backend support for etm-perf

2017-11-07 Thread Mike Leach
Hi Suzuki, Mathieu, A follow up on Dragonboard issues... = Using Suzukis debug code and some of my own home spun updates I've got the following logging out of a typical ETR-SG session from the DB410. Session initiated using command line './perf record -e cs_etm/@826000.etr/ --per-thread sort

Re: [PATCH 17/17] coresight perf: Add ETR backend support for etm-perf

2017-11-07 Thread Suzuki K Poulose
On 07/11/17 00:24, Mathieu Poirier wrote: On Thu, Oct 19, 2017 at 06:15:53PM +0100, Suzuki K Poulose wrote: Add necessary support for using ETR as a sink in ETM perf tracing. We try make the best use of the available modes of buffers to try and avoid software double buffering. We can use the pe

Re: [PATCH 17/17] coresight perf: Add ETR backend support for etm-perf

2017-11-06 Thread Mathieu Poirier
On Thu, Oct 19, 2017 at 06:15:53PM +0100, Suzuki K Poulose wrote: > Add necessary support for using ETR as a sink in ETM perf tracing. > We try make the best use of the available modes of buffers to > try and avoid software double buffering. > > We can use the perf ring buffer for ETR directly if

[PATCH 17/17] coresight perf: Add ETR backend support for etm-perf

2017-10-19 Thread Suzuki K Poulose
Add necessary support for using ETR as a sink in ETM perf tracing. We try make the best use of the available modes of buffers to try and avoid software double buffering. We can use the perf ring buffer for ETR directly if all of the conditions below are met : 1) ETR is DMA coherent 2) perf is us