On Sunday 17 April 2016 01:01 AM, David Lechner wrote:
>> +static int da850_async3_set_parent(struct clk *clk, struct clk *parent)
>> +{
>> +u32 val;
>> +
>> +val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
>> +
>> +/* Set the USB 1.1 PHY clock mux based on the parent clock. */
>
On 04/14/2016 02:13 PM, David Lechner wrote:
The da850 family of processors has an async3 clock domain that can be
muxed to either pll0_sysclk2 or pll1_sysclk2. Now that the davinci clocks
have a set_parent callback, we can use this to control the async3 mux
instead of a stand-alone function.
Th
The da850 family of processors has an async3 clock domain that can be
muxed to either pll0_sysclk2 or pll1_sysclk2. Now that the davinci clocks
have a set_parent callback, we can use this to control the async3 mux
instead of a stand-alone function.
This adds a new async3_clk and sets the appropria
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