No longer need cfgrdX and cfgwrX since we have separate defines for
TLP_CFG*_DW0 and S10_TLP_CFG*_DW0, so remove them.
Signed-off-by: Ley Foon Tan <ley.foon....@intel.com>
---
drivers/pci/controller/pcie-altera.c | 33 +++++++---------------------
1 file changed, 8 insertions(+), 25 deletions(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 047bcc214f9b..d96980a4e327 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -58,20 +58,20 @@
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
#define TLP_CFGRD_DW0(pcie, bus) \
- ((((bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \
- : pcie->pcie_data->cfgrd1) << 24) | \
+ ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
+ : TLP_FMTTYPE_CFGRD1) << 24) | \
TLP_PAYLOAD_SIZE)
#define TLP_CFGWR_DW0(pcie, bus) \
- ((((bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
- : pcie->pcie_data->cfgwr1) << 24) | \
+ ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
+ : TLP_FMTTYPE_CFGWR1) << 24) | \
TLP_PAYLOAD_SIZE)
#define S10_TLP_CFGRD_DW0(pcie, bus) \
- (((((bus) > S10_RP_SECONDARY(pcie)) ? pcie->pcie_data->cfgrd0 \
- : pcie->pcie_data->cfgrd1) << 24) | \
+ (((((bus) > S10_RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1 \
+ : TLP_FMTTYPE_CFGRD0) << 24) | \
TLP_PAYLOAD_SIZE)
#define S10_TLP_CFGWR_DW0(pcie, bus) \
- (((((bus) > S10_RP_SECONDARY(pcie)) ? pcie->pcie_data->cfgwr0 \
- : pcie->pcie_data->cfgwr1) << 24) | \
+ (((((bus) > S10_RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1 \
+ : TLP_FMTTYPE_CFGWR0) << 24) | \
TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
@@ -87,11 +87,6 @@
#define DWORD_MASK 3
-#define S10_TLP_FMTTYPE_CFGRD0 0x05
-#define S10_TLP_FMTTYPE_CFGRD1 0x04
-#define S10_TLP_FMTTYPE_CFGWR0 0x45
-#define S10_TLP_FMTTYPE_CFGWR1 0x44
-
enum altera_pcie_version {
ALTERA_PCIE_V1 = 0,
ALTERA_PCIE_V2,
@@ -124,10 +119,6 @@ struct altera_pcie_data {
const struct altera_pcie_ops *ops;
enum altera_pcie_version version;
u32 cap_offset; /* PCIe capability structure register offset */
- u32 cfgrd0;
- u32 cfgrd1;
- u32 cfgwr0;
- u32 cfgwr1;
};
struct tlp_rp_regpair_t {
@@ -784,20 +775,12 @@ static const struct altera_pcie_data altera_pcie_1_0_data
= {
.ops = &altera_pcie_ops_1_0,
.cap_offset = 0x80,
.version = ALTERA_PCIE_V1,
- .cfgrd0 = TLP_FMTTYPE_CFGRD0,
- .cfgrd1 = TLP_FMTTYPE_CFGRD1,
- .cfgwr0 = TLP_FMTTYPE_CFGWR0,
- .cfgwr1 = TLP_FMTTYPE_CFGWR1,
};
static const struct altera_pcie_data altera_pcie_2_0_data = {
.ops = &altera_pcie_ops_2_0,
.version = ALTERA_PCIE_V2,
.cap_offset = 0x70,
- .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0,
- .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1,
- .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0,
- .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1,
};
static const struct of_device_id altera_pcie_of_match[] = {
--
2.19.0
