Re: [linux-sunxi] [PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs

2017-08-14 Thread Chen-Yu Tsai
On Fri, Aug 11, 2017 at 10:27 PM, Icenowy Zheng wrote: > The pin controller of H5 has three IRQs at the chip's GIC, which > represents three banks of pinctrl IRQs. However, the device tree used to > miss the third IRQ of the pin controller, which makes the PG bank IRQ > not

Re: [linux-sunxi] [PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs

2017-08-14 Thread Chen-Yu Tsai
On Fri, Aug 11, 2017 at 10:27 PM, Icenowy Zheng wrote: > The pin controller of H5 has three IRQs at the chip's GIC, which > represents three banks of pinctrl IRQs. However, the device tree used to > miss the third IRQ of the pin controller, which makes the PG bank IRQ > not usable. > > Add the

[PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs

2017-08-11 Thread Icenowy Zheng
The pin controller of H5 has three IRQs at the chip's GIC, which represents three banks of pinctrl IRQs. However, the device tree used to miss the third IRQ of the pin controller, which makes the PG bank IRQ not usable. Add the missing IRQ to the pinctrl node. Fixes: 4e36de179f27 ("arm64:

[PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs

2017-08-11 Thread Icenowy Zheng
The pin controller of H5 has three IRQs at the chip's GIC, which represents three banks of pinctrl IRQs. However, the device tree used to miss the third IRQ of the pin controller, which makes the PG bank IRQ not usable. Add the missing IRQ to the pinctrl node. Fixes: 4e36de179f27 ("arm64: