On Tue, 8 Oct 2019 at 11:35, Andrew Jeffery wrote:
>
> RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
> single gate for each MAC.
>
> Signed-off-by: Andrew Jeffery
We could have mac12rclk and mac34rclk described in the device tree, as
was mentioned in previous reviews
RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
single gate for each MAC.
Signed-off-by: Andrew Jeffery
---
drivers/clk/clk-ast2600.c | 47 ++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-ast2600.c
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