Re: [PATCH 2/2] clk: mediatek: fix PWM clock source by adding a fixed-factor clock

Quoting sean.w...@mediatek.com (2018-02-28 19:27:51) > From: Sean Wang > > The clock for which all PWM devices on MT7623 or MT2701 actually depending > on has to be divided by four from its parent clock axi_sel in the clock > path prior to PWM devices. > > Consequently,

Re: [PATCH 2/2] clk: mediatek: fix PWM clock source by adding a fixed-factor clock

Quoting sean.w...@mediatek.com (2018-02-28 19:27:51) > From: Sean Wang > > The clock for which all PWM devices on MT7623 or MT2701 actually depending > on has to be divided by four from its parent clock axi_sel in the clock > path prior to PWM devices. > > Consequently, adding a fixed-factor

[PATCH 2/2] clk: mediatek: fix PWM clock source by adding a fixed-factor clock

From: Sean Wang The clock for which all PWM devices on MT7623 or MT2701 actually depending on has to be divided by four from its parent clock axi_sel in the clock path prior to PWM devices. Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of clock

[PATCH 2/2] clk: mediatek: fix PWM clock source by adding a fixed-factor clock

From: Sean Wang The clock for which all PWM devices on MT7623 or MT2701 actually depending on has to be divided by four from its parent clock axi_sel in the clock path prior to PWM devices. Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of clock axi_sel allows that PWM