On Thu, Jun 27, 2019 at 6:59 PM Rob Herring wrote:
>
> On Thu, Jun 27, 2019 at 1:40 AM Daniel Baluta wrote:
> >
> >
> >
> > > > > > + mboxes:
> > > > > > +description:
> > > > > > + List of phandle of 2 MU channels for TXDB, 2 MU channels for
> > > > > > RXDB
> > > > > > + (see
On Thu, Jun 27, 2019 at 1:40 AM Daniel Baluta wrote:
>
>
>
> > > > > + mboxes:
> > > > > +description:
> > > > > + List of phandle of 2 MU channels for TXDB, 2 MU channels for
> > > > > RXDB
> > > > > + (see mailbox/fsl,mu.txt)
> > > > > +maxItems: 1
> > > >
> > > > Should be
> > > > + mboxes:
> > > > +description:
> > > > + List of phandle of 2 MU channels for TXDB, 2 MU channels for RXDB
> > > > + (see mailbox/fsl,mu.txt)
> > > > +maxItems: 1
> > >
> > > Should be 4?
> >
> > Actually is just a list with 1 item. I think is the terminology:
> >
> >
On Wed, Jun 26, 2019 at 8:49 AM Daniel Baluta wrote:
>
> Hi Rob,
>
> This is my first time documenting the bindings using the
> new yaml format so thanks for your patience and explanations!
>
> On Fri, Jun 14, 2019 at 5:53 PM Rob Herring wrote:
> >
> > On Fri, Jun 14, 2019 at 2:15 AM wrote:
> >
Hi Rob,
This is my first time documenting the bindings using the
new yaml format so thanks for your patience and explanations!
On Fri, Jun 14, 2019 at 5:53 PM Rob Herring wrote:
>
> On Fri, Jun 14, 2019 at 2:15 AM wrote:
> >
> > From: Daniel Baluta
> >
> > DSP IPC is the layer that allows the
On Fri, Jun 14, 2019 at 2:15 AM wrote:
>
> From: Daniel Baluta
>
> DSP IPC is the layer that allows the Host CPU to communicate
> with DSP firmware.
> DSP is part of some i.MX8 boards (e.g i.MX8QM, i.MX8QXP)
>
> Signed-off-by: Daniel Baluta
> ---
> .../bindings/arm/freescale/fsl,dsp.yaml
From: Daniel Baluta
DSP IPC is the layer that allows the Host CPU to communicate
with DSP firmware.
DSP is part of some i.MX8 boards (e.g i.MX8QM, i.MX8QXP)
Signed-off-by: Daniel Baluta
---
.../bindings/arm/freescale/fsl,dsp.yaml | 43 +++
1 file changed, 43
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