On 05/05/16 10:48, Jim Quinlan wrote:
>>> Why is this?
>>
>> This is so we do not end-up programming the PCIe RC which is agnostic of
>> the number of
>
> I believe this code is still around for folks passing us a device tree
> with lacking information. It should be removed.
I have actually rewo
On Wed, May 4, 2016 at 3:36 PM, Florian Fainelli wrote:
> On 03/05/16 02:57, Arnd Bergmann wrote:
>>> +static const struct pcie_cfg_data generic_cfg = {
>>> +.offsets= pcie_offsets,
>>> +.type = GENERIC,
>>> +};
>>
>> The way you access the config space here seems very in
On Wednesday 04 May 2016 13:07:20 Florian Fainelli wrote:
> On 04/05/16 12:56, Arnd Bergmann wrote:
> > On Wednesday 04 May 2016 12:36:17 Florian Fainelli wrote:
> >> On 03/05/16 02:57, Arnd Bergmann wrote:
> >> How about introducing helper functions but keeping the same set of
> >> read/write pci_
On 04/05/16 12:56, Arnd Bergmann wrote:
> On Wednesday 04 May 2016 12:36:17 Florian Fainelli wrote:
>> On 03/05/16 02:57, Arnd Bergmann wrote:
+static const struct pcie_cfg_data generic_cfg = {
+ .offsets= pcie_offsets,
+ .type = GENERIC,
+};
>>>
>>> The way
On Wednesday 04 May 2016 12:36:17 Florian Fainelli wrote:
> On 03/05/16 02:57, Arnd Bergmann wrote:
> >> +static const struct pcie_cfg_data generic_cfg = {
> >> + .offsets= pcie_offsets,
> >> + .type = GENERIC,
> >> +};
> >
> > The way you access the config space here seems ver
On 03/05/16 02:57, Arnd Bergmann wrote:
>> +static const struct pcie_cfg_data generic_cfg = {
>> +.offsets= pcie_offsets,
>> +.type = GENERIC,
>> +};
>
> The way you access the config space here seems very indirect. I'd
> suggest instead writing two sets of pci_ops, with
On Monday 02 May 2016 18:25:49 Florian Fainelli wrote:
> +/* Helper macros for reading registers varying from chip-to-chip */
> +#define IDX_ADDR(pcie) ((pcie->base) + \
> + pcie->reg_offsets[EXT_CFG_INDEX])
> +#define DATA_ADDR(pcie)
From: Jim Quinlan
This patch adds support for Broadcom's STB SoC PCIE root complex
controller. This controller can be found in MIPS-based chips such as
BCM7425, 7429 and 7435 and ARM-based SoCs such as BCM7445.
This driver enables support for MSI, regulators that need to be turned
on prior to sc
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