Re: [PATCH 2/2] perf/x86/intel: Add Tremont core PMU support

2019-04-10 Thread Liang, Kan
On 4/10/2019 3:51 AM, Peter Zijlstra wrote: On Tue, Apr 09, 2019 at 06:10:00PM -0700, kan.li...@linux.intel.com wrote: The generic purpose counter 0 and fixed counter 0 have less skid. Force :ppp events on generic purpose counter 0. Force instruction:ppp always on fixed counter 0.

Re: [PATCH 2/2] perf/x86/intel: Add Tremont core PMU support

2019-04-10 Thread Peter Zijlstra
On Tue, Apr 09, 2019 at 06:10:00PM -0700, kan.li...@linux.intel.com wrote: > The generic purpose counter 0 and fixed counter 0 have less skid. > Force :ppp events on generic purpose counter 0. > Force instruction:ppp always on fixed counter 0. > +static struct event_constraint * >

[PATCH 2/2] perf/x86/intel: Add Tremont core PMU support

2019-04-09 Thread kan . liang
From: Kan Liang Add perf core PMU support for Intel Tremont CPU. The init code is based on Goldmont plus. The generic purpose counter 0 and fixed counter 0 have less skid. Force :ppp events on generic purpose counter 0. Force instruction:ppp always on fixed counter 0. Updates LLC cache event