On Fri, Jul 20, 2018 at 6:38 PM, Daniel Kurtz wrote:
> Sounds reasonable. How about:
>
> - /* Clear interrupt.
> -* We must read the pin register again, in case the
> -* value was changed while executing
> -
Hi Daniel,
On Tue, Jul 17, 2018 at 6:30 AM Daniel Drake wrote:
>
> On Mon, Jul 16, 2018 at 7:57 PM, Daniel Kurtz wrote:
> > Commit 6afb10267c1692 ("pinctrl/amd: fix masking of GPIO interrupts")
> > changed to the clearing of interrupt status bits to a RMW in a critical
> > section. This works,
On Mon, Jul 16, 2018 at 7:57 PM, Daniel Kurtz wrote:
> Commit 6afb10267c1692 ("pinctrl/amd: fix masking of GPIO interrupts")
> changed to the clearing of interrupt status bits to a RMW in a critical
> section. This works, but is a bit overkill.
>
> The relevant interrupt/wake status bits are in t
Commit 6afb10267c1692 ("pinctrl/amd: fix masking of GPIO interrupts")
changed to the clearing of interrupt status bits to a RMW in a critical
section. This works, but is a bit overkill.
The relevant interrupt/wake status bits are in the Most Significant Byte
of a 32-bit word. These two are the o
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