On Thursday 13 April 2017 08:57 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Apr 13, 2017 at 07:40:28PM +0530, Laxman Dewangan wrote:
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
For Tegra210, it is 38.4MHz.
On Thursday 13 April 2017 08:57 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Apr 13, 2017 at 07:40:28PM +0530, Laxman Dewangan wrote:
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
For Tegra210, it is 38.4MHz.
On Thu, Apr 13, 2017 at 07:40:28PM +0530, Laxman Dewangan wrote:
> The PWM hardware IP is taped-out with different maximum frequency
> on different SoCs.
>
> From HW team:
> For Tegra210, it is 38.4MHz.
> For Tegra186, it is 102MHz.
>
> Add support to limit the clock source frequency
On Thu, Apr 13, 2017 at 07:40:28PM +0530, Laxman Dewangan wrote:
> The PWM hardware IP is taped-out with different maximum frequency
> on different SoCs.
>
> From HW team:
> For Tegra210, it is 38.4MHz.
> For Tegra186, it is 102MHz.
>
> Add support to limit the clock source frequency
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
>From HW team:
For Tegra210, it is 38.4MHz.
For Tegra186, it is 102MHz.
Add support to limit the clock source frequency to the maximum IP
supported frequency. Provide these values via SoC
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
>From HW team:
For Tegra210, it is 38.4MHz.
For Tegra186, it is 102MHz.
Add support to limit the clock source frequency to the maximum IP
supported frequency. Provide these values via SoC
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