(sorry for malformed email but I didn't want to hold this patch longer)
On 14/04/2017 at 10:22:43 +0200, Quentin Schulz wrote:
> This adds deepest (Backup+Self-Refresh) PM support to the ATMEL SAMA5D2
> SoC's SPI controller.
>
> When resuming from deepest state, it is required to restore MR regist
On 14/04/2017 at 10:22:43 +0200, Quentin Schulz wrote:
> This adds deepest (Backup+Self-Refresh) PM support to the ATMEL SAMA5D2
> SoC's SPI controller.
>
> When resuming from deepest state, it is required to restore MR register
> as the registers are lost since VDD core has been shut down when
>
This adds deepest (Backup+Self-Refresh) PM support to the ATMEL SAMA5D2
SoC's SPI controller.
When resuming from deepest state, it is required to restore MR register
as the registers are lost since VDD core has been shut down when
entering deepest state on the SAMA5D2.
Signed-off-by: Quentin Schu
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