Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On Tue, Oct 27, 2015 at 11:48:02AM -0500, Aravind Gopalakrishnan wrote: > Forgot to ask earlier about this- > Shall I still sanitize the comments to say "AMD extended features 1" for > 0x8001,ecx > and "AMD extended features 2" for 0x8008, ebx? Just use the cpufeature.h nomenclature: /*

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On 10/26/2015 8:09 PM, Borislav Petkov wrote: you called it "AMD extended features 2" - then those should really go into into the x86_capability array, i.e., like you've done it in your initial version. So please fix the SOB chain of your initial patch and send that one out. Forgot to ask

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On 10/26/2015 8:09 PM, Borislav Petkov wrote: On Mon, Oct 26, 2015 at 05:50:47PM -0500, Aravind Gopalakrishnan wrote: How do you prefer a V2 for this to be sent though- Shall I wait until your fixes are in tip.git and resend? Or send a V2 on top of current tip.git? Actually, I just showed it

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On 10/26/2015 8:09 PM, Borislav Petkov wrote: On Mon, Oct 26, 2015 at 05:50:47PM -0500, Aravind Gopalakrishnan wrote: How do you prefer a V2 for this to be sent though- Shall I wait until your fixes are in tip.git and resend? Or send a V2 on top of current tip.git? Actually, I just showed it

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On 10/26/2015 8:09 PM, Borislav Petkov wrote: you called it "AMD extended features 2" - then those should really go into into the x86_capability array, i.e., like you've done it in your initial version. So please fix the SOB chain of your initial patch and send that one out. Forgot to ask

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On Tue, Oct 27, 2015 at 11:48:02AM -0500, Aravind Gopalakrishnan wrote: > Forgot to ask earlier about this- > Shall I still sanitize the comments to say "AMD extended features 1" for > 0x8001,ecx > and "AMD extended features 2" for 0x8008, ebx? Just use the cpufeature.h nomenclature: /*

Re: [RFC PATCH] x86/cpu: Move sparsely used bit leafs into scattered features (was: Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature)

On Mon, Oct 26, 2015 at 07:56:06PM -0700, Andy Lutomirski wrote: > How few features in one leaf do we need before calling it scattered > makes sense? These four might make sense to keep as is... Actually, according to hpa, all those leafs will be filled out gradually as they're apparently going

Re: [RFC PATCH] x86/cpu: Move sparsely used bit leafs into scattered features (was: Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature)

On Mon, Oct 26, 2015 at 2:01 PM, Borislav Petkov wrote: > On Mon, Oct 26, 2015 at 09:22:50PM +0100, Borislav Petkov wrote: >> And btw, those Intel QoS single bit defines and the XSAVE stuff there >> should move to that function too - that's a pure waste having them in >> the cap_flags array. I'll

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On Mon, Oct 26, 2015 at 05:50:47PM -0500, Aravind Gopalakrishnan wrote: > How do you prefer a V2 for this to be sent though- > Shall I wait until your fixes are in tip.git and resend? > Or send a V2 on top of current tip.git? Actually, I just showed it to hpa and he says those CPUID leafs are

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On 10/26/2015 3:22 PM, Borislav Petkov wrote: On Mon, Oct 26, 2015 at 10:12:59AM -0500, Aravind Gopalakrishnan wrote: For large part yes, wrapped code in patch form with commit message etc. And modified comment a little bit. Does that still require his address in "From"? Yes, because it

[RFC PATCH] x86/cpu: Move sparsely used bit leafs into scattered features (was: Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature)

On Mon, Oct 26, 2015 at 09:22:50PM +0100, Borislav Petkov wrote: > And btw, those Intel QoS single bit defines and the XSAVE stuff there > should move to that function too - that's a pure waste having them in > the cap_flags array. I'll fix that. I.e., something like that (I'm jetlagged and I

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On Mon, Oct 26, 2015 at 10:12:59AM -0500, Aravind Gopalakrishnan wrote: > For large part yes, wrapped code in patch form with commit message etc. > And modified comment a little bit. > > Does that still require his address in "From"? Yes, because it sounds like he was the author of the original

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

(removing peter.p.waskiewicz...@intel.com as email bounced) On 10/25/2015 5:37 AM, Borislav Petkov wrote: On Fri, Oct 23, 2015 at 06:18:33AM -0500, Aravind Gopalakrishnan wrote: CLZERO instruction introduced in AMD Fam17h processors zero's out a 64 byte cache line specified in RAX. Add the

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On 10/25/2015 5:37 AM, Borislav Petkov wrote: On Fri, Oct 23, 2015 at 06:18:33AM -0500, Aravind Gopalakrishnan wrote: CLZERO instruction introduced in AMD Fam17h processors zero's out a 64 byte cache line specified in RAX. Add the bit here to allow /proc/cpuinfo to list the feature

[RFC PATCH] x86/cpu: Move sparsely used bit leafs into scattered features (was: Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature)

On Mon, Oct 26, 2015 at 09:22:50PM +0100, Borislav Petkov wrote: > And btw, those Intel QoS single bit defines and the XSAVE stuff there > should move to that function too - that's a pure waste having them in > the cap_flags array. I'll fix that. I.e., something like that (I'm jetlagged and I

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On Mon, Oct 26, 2015 at 10:12:59AM -0500, Aravind Gopalakrishnan wrote: > For large part yes, wrapped code in patch form with commit message etc. > And modified comment a little bit. > > Does that still require his address in "From"? Yes, because it sounds like he was the author of the original

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On Mon, Oct 26, 2015 at 05:50:47PM -0500, Aravind Gopalakrishnan wrote: > How do you prefer a V2 for this to be sent though- > Shall I wait until your fixes are in tip.git and resend? > Or send a V2 on top of current tip.git? Actually, I just showed it to hpa and he says those CPUID leafs are

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On 10/26/2015 3:22 PM, Borislav Petkov wrote: On Mon, Oct 26, 2015 at 10:12:59AM -0500, Aravind Gopalakrishnan wrote: For large part yes, wrapped code in patch form with commit message etc. And modified comment a little bit. Does that still require his address in "From"? Yes, because it

Re: [RFC PATCH] x86/cpu: Move sparsely used bit leafs into scattered features (was: Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature)

On Mon, Oct 26, 2015 at 07:56:06PM -0700, Andy Lutomirski wrote: > How few features in one leaf do we need before calling it scattered > makes sense? These four might make sense to keep as is... Actually, according to hpa, all those leafs will be filled out gradually as they're apparently going

Re: [RFC PATCH] x86/cpu: Move sparsely used bit leafs into scattered features (was: Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature)

On Mon, Oct 26, 2015 at 2:01 PM, Borislav Petkov wrote: > On Mon, Oct 26, 2015 at 09:22:50PM +0100, Borislav Petkov wrote: >> And btw, those Intel QoS single bit defines and the XSAVE stuff there >> should move to that function too - that's a pure waste having them in >> the

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

(removing peter.p.waskiewicz...@intel.com as email bounced) On 10/25/2015 5:37 AM, Borislav Petkov wrote: On Fri, Oct 23, 2015 at 06:18:33AM -0500, Aravind Gopalakrishnan wrote: CLZERO instruction introduced in AMD Fam17h processors zero's out a 64 byte cache line specified in RAX. Add the

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On 10/25/2015 5:37 AM, Borislav Petkov wrote: On Fri, Oct 23, 2015 at 06:18:33AM -0500, Aravind Gopalakrishnan wrote: CLZERO instruction introduced in AMD Fam17h processors zero's out a 64 byte cache line specified in RAX. Add the bit here to allow /proc/cpuinfo to list the feature

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On Fri, Oct 23, 2015 at 06:18:33AM -0500, Aravind Gopalakrishnan wrote: > CLZERO instruction introduced in AMD Fam17h processors > zero's out a 64 byte cache line specified in RAX. > > Add the bit here to allow /proc/cpuinfo to list the feature > > Signed-off-by: Wan Zongshun > Signed-off-by:

Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature

On Fri, Oct 23, 2015 at 06:18:33AM -0500, Aravind Gopalakrishnan wrote: > CLZERO instruction introduced in AMD Fam17h processors > zero's out a 64 byte cache line specified in RAX. > > Add the bit here to allow /proc/cpuinfo to list the feature > > Signed-off-by: Wan Zongshun

[PATCH 2/2] x86/cpufeature: Add CLZERO feature

CLZERO instruction introduced in AMD Fam17h processors zero's out a 64 byte cache line specified in RAX. Add the bit here to allow /proc/cpuinfo to list the feature Signed-off-by: Wan Zongshun Signed-off-by: Aravind Gopalakrishnan --- arch/x86/include/asm/cpufeature.h | 5 -

[PATCH 2/2] x86/cpufeature: Add CLZERO feature

CLZERO instruction introduced in AMD Fam17h processors zero's out a 64 byte cache line specified in RAX. Add the bit here to allow /proc/cpuinfo to list the feature Signed-off-by: Wan Zongshun Signed-off-by: Aravind Gopalakrishnan ---