Hi Suravee,
On Thu, Sep 18 2014 at 03:14:46 AM, "suravee.suthikulpa...@amd.com"
wrote:
> From: Suravee Suthikulpanit
>
> ARM GICv2m specification extends GICv2 to support MSI(-X) with
> a new set of register frame. This patch introduces support for
> the non-secure GICv2m register frame.
Hi Suravee,
On Thu, Sep 18 2014 at 03:14:46 AM, suravee.suthikulpa...@amd.com
suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch
4 matches
Mail list logo