On 11/12/2012 10:03 PM, Laxman Dewangan wrote:
> Add OF_DEV_AUXDATA for sflash controller driver for Tegra20
> board dt files.
> Set the parent clock of sflash controller to PLLP and configure
> clock to 20MHz.
Thanks, applied to Tegra's for-3.8/soc branch.
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Add OF_DEV_AUXDATA for sflash controller driver for Tegra20
board dt files.
Set the parent clock of sflash controller to PLLP and configure
clock to 20MHz.
Signed-off-by: Laxman Dewangan
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arch/arm/mach-tegra/board-dt-tegra20.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
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