Re: [PATCH 2/3] MIPS: enforce LL-SC loop enclosing with SYNC (ACQUIRE and RELEASE)

On 06/02/2015 04:39 AM, James Hogan wrote: Hi Leonid, On 02/06/15 01:09, Leonid Yegoshin wrote: CPUs may occasionally have problems in accordance with HW team. "have problems in accordance with HW team" is a bit confusing. What do you mean? I wrote about memory barriers and problems may hap

Re: [PATCH 2/3] MIPS: enforce LL-SC loop enclosing with SYNC (ACQUIRE and RELEASE)

Hi Leonid, On 02/06/15 01:09, Leonid Yegoshin wrote: > Many MIPS32 R2 and all MIPS R6 CPUs are out of order execution, so it > needs memory barriers in SMP environment. However, past cores may have > a pipeline short enough to ignore that requirements and problem may > never occurs until recently.

[PATCH 2/3] MIPS: enforce LL-SC loop enclosing with SYNC (ACQUIRE and RELEASE)

Many MIPS32 R2 and all MIPS R6 CPUs are out of order execution, so it needs memory barriers in SMP environment. However, past cores may have a pipeline short enough to ignore that requirements and problem may never occurs until recently. This patch gives an option to enclose LL-SC loops by SYNC ba