Three clock drivers are used by Stratix 10, Agilex and N5X, so use separate dedicated Kconfig entry to get rid of duplicated Makefile lines. This will also allow later compile testing.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlow...@canonical.com> --- drivers/clk/socfpga/Kconfig | 7 +++++++ drivers/clk/socfpga/Makefile | 3 +-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig index cae6fd9fac64..4922cc35f4cc 100644 --- a/drivers/clk/socfpga/Kconfig +++ b/drivers/clk/socfpga/Kconfig @@ -1,6 +1,13 @@ # SPDX-License-Identifier: GPL-2.0 +config COMMON_CLK_STRATIX10 + bool + # Intel Stratix / Agilex / N5X clock controller support + default y if ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10 + depends on ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10 + config COMMON_CLK_AGILEX bool # Intel Agilex / N5X clock controller support default y if ARCH_AGILEX || ARCH_N5X depends on ARCH_AGILEX || ARCH_N5X + select COMMON_CLK_STRATIX10 diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index e3614f758184..8a875de971fc 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -2,6 +2,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o -obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o +obj-$(CONFIG_COMMON_CLK_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o obj-$(CONFIG_COMMON_CLK_AGILEX) += clk-agilex.o -obj-$(CONFIG_COMMON_CLK_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o -- 2.25.1