[PATCH 2/3] powerpc: make copyuser_power7.S 64-byte cacheline friendly

The innermost copyloops were optimized for POWER7's 128-byte cacheline. This patch adds optimization for the e6500, which has a 64-byte cacheline. We basically do this by stripping loop bodies using L1_CACHE_BYTES ifdeferry, replace 128 with L1_CACHE_BYTES, and 7's with L1_CACHE_SHIFTs. We also

[PATCH 2/3] powerpc: make copyuser_power7.S 64-byte cacheline friendly

The innermost copyloops were optimized for POWER7's 128-byte cacheline. This patch adds optimization for the e6500, which has a 64-byte cacheline. We basically do this by stripping loop bodies using L1_CACHE_BYTES ifdeferry, replace 128 with L1_CACHE_BYTES, and 7's with L1_CACHE_SHIFTs. We also