Hi,
On Fri, Jan 20, 2017 at 09:50:22PM +0530, Afzal Mohammed wrote:
> On Thu, Jan 19, 2017 at 01:59:09PM +, Vladimir Murzin wrote:
> > You can use
> >
> > cpuid_feature_extract(CPUID_EXT_PFR1, 4)
> >
> > and add a comment explaining what we are looking for and why.
W.r.t comments,
Hi,
On Thu, Jan 19, 2017 at 01:59:09PM +, Vladimir Murzin wrote:
> On 18/01/17 20:38, afzal mohammed wrote:
> > +#define ID_PFR1_SE (0x3 << 4) /* Security extension enable bits */
>
> This bitfiled is 4 bits wide.
Since only 2 LSb's out of the 4 were enough to detect whether security
e
Hi,
On 18/01/17 20:38, afzal mohammed wrote:
> No-MMU dynamic exception base address configuration on CP15
> processors. In the case of low vectors, decision based on whether
> security extensions are enabled & whether remap vectors to RAM
> CONFIG option is selected.
>
> For no-MMU without CP15,
No-MMU dynamic exception base address configuration on CP15
processors. In the case of low vectors, decision based on whether
security extensions are enabled & whether remap vectors to RAM
CONFIG option is selected.
For no-MMU without CP15, current default value of 0x0 is retained.
Signed-off-by:
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