Re: [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised

2015-12-02 Thread Stanimir Varbanov
On 12/02/2015 03:05 PM, Arnd Bergmann wrote: > On Wednesday 02 December 2015 14:56:57 Stanimir Varbanov wrote: >> On 12/01/2015 12:29 PM, Arnd Bergmann wrote: >>> On Tuesday 01 December 2015 11:14:57 Stanimir Varbanov wrote: + if (srcs & BAM_IRQ) { clr_mask = readl_r

Re: [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised

2015-12-02 Thread Arnd Bergmann
On Wednesday 02 December 2015 14:56:57 Stanimir Varbanov wrote: > On 12/01/2015 12:29 PM, Arnd Bergmann wrote: > > On Tuesday 01 December 2015 11:14:57 Stanimir Varbanov wrote: > >> + if (srcs & BAM_IRQ) { > >> clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); > >>

Re: [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised

2015-12-02 Thread Stanimir Varbanov
On 12/01/2015 12:29 PM, Arnd Bergmann wrote: > On Tuesday 01 December 2015 11:14:57 Stanimir Varbanov wrote: >> + if (srcs & BAM_IRQ) { >> clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); >> >> - /* don't allow reorder of the various accesses to the BAM regis

Re: [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised

2015-12-01 Thread Andy Gross
On Tue, Dec 01, 2015 at 11:14:57AM +0200, Stanimir Varbanov wrote: > Currently we write BAM_IRQ_CLR register with zero even when no > BAM_IRQ occured. This write has some bad side effects when the > BAM instance is for the crypto engine. In case of crypto engine > some of the BAM registers are xPU

Re: [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised

2015-12-01 Thread Arnd Bergmann
On Tuesday 01 December 2015 11:14:57 Stanimir Varbanov wrote: > + if (srcs & BAM_IRQ) { > clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); > > - /* don't allow reorder of the various accesses to the BAM registers */ > - mb(); > + /* > +

[PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised

2015-12-01 Thread Stanimir Varbanov
Currently we write BAM_IRQ_CLR register with zero even when no BAM_IRQ occured. This write has some bad side effects when the BAM instance is for the crypto engine. In case of crypto engine some of the BAM registers are xPU protected and they cannot be controlled by the driver. Signed-off-by: Stan