[PATCH 2/4 v11] clk, highbank: Prevent glitches in non-bypass reset mode

The highbank clock will glitch with the current code if the clock rate is reset without relocking the PLL. Program the PLL correctly to prevent glitches. Signed-off-by: Mark Langsdorf Signed-off-by: Rob Herring Acked-by: Mike Turquette --- Changes from v6, v7, v8, v9, v10 None. Changes

[PATCH 2/4 v11] clk, highbank: Prevent glitches in non-bypass reset mode

The highbank clock will glitch with the current code if the clock rate is reset without relocking the PLL. Program the PLL correctly to prevent glitches. Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com Signed-off-by: Rob Herring rob.herr...@calxeda.com Acked-by: Mike Turquette