[PATCH 2/5] clk: at91: rework PLL rate calculation

The AT91 PLL rate configuration is done by configuring a multiplier/divider pair. The previous calculation was over-complicated (and apparently buggy). Simplify the implementation and add some comments to explain what is done here. Signed-off-by: Boris BREZILLON Reported-by: Gaël PORTAY ---

[PATCH 2/5] clk: at91: rework PLL rate calculation

The AT91 PLL rate configuration is done by configuring a multiplier/divider pair. The previous calculation was over-complicated (and apparently buggy). Simplify the implementation and add some comments to explain what is done here. Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com