Hi Will,
On 2021/1/8 22:09, Will Deacon wrote:
Hi Lu,
On Fri, Jan 08, 2021 at 07:52:47AM +0800, Lu Baolu wrote:
On 2021/1/6 9:09, Lu Baolu wrote:
On 2021/1/6 3:03, Will Deacon wrote:
On Thu, Dec 31, 2020 at 08:53:20AM +0800, Lu Baolu wrote:
@@ -170,6 +172,22 @@ static void intel_flush_svm_r
Hi Lu,
On Fri, Jan 08, 2021 at 07:52:47AM +0800, Lu Baolu wrote:
> On 2021/1/6 9:09, Lu Baolu wrote:
> > On 2021/1/6 3:03, Will Deacon wrote:
> > > On Thu, Dec 31, 2020 at 08:53:20AM +0800, Lu Baolu wrote:
> > > > @@ -170,6 +172,22 @@ static void intel_flush_svm_range_dev
> > > > (struct intel_svm
Hi Will,
On 2021/1/6 9:09, Lu Baolu wrote:
Hi Will,
Happy New Year!
On 2021/1/6 3:03, Will Deacon wrote:
On Thu, Dec 31, 2020 at 08:53:20AM +0800, Lu Baolu wrote:
The VT-d hardware will ignore those Addr bits which have been masked by
the AM field in the PASID-based-IOTLB invalidation descri
Hi Will,
Happy New Year!
On 2021/1/6 3:03, Will Deacon wrote:
On Thu, Dec 31, 2020 at 08:53:20AM +0800, Lu Baolu wrote:
The VT-d hardware will ignore those Addr bits which have been masked by
the AM field in the PASID-based-IOTLB invalidation descriptor. As the
result, if the starting address
On Thu, Dec 31, 2020 at 08:53:20AM +0800, Lu Baolu wrote:
> The VT-d hardware will ignore those Addr bits which have been masked by
> the AM field in the PASID-based-IOTLB invalidation descriptor. As the
> result, if the starting address in the descriptor is not aligned with
> the address mask, som
The VT-d hardware will ignore those Addr bits which have been masked by
the AM field in the PASID-based-IOTLB invalidation descriptor. As the
result, if the starting address in the descriptor is not aligned with
the address mask, some IOTLB caches might not invalidate. Hence people
will see below e
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