On 6/14/2018 10:09 PM, Rob Herring wrote:
On Thu, Jun 14, 2018 at 2:40 AM, yixin zhu wrote:
On 6/13/2018 6:37 AM, Rob Herring wrote:
On Tue, Jun 12, 2018 at 01:40:29PM +0800, Songjun Wu wrote:
From: Yixin Zhu
PLL of GRX500 provide clock to DDR, CPU, and peripherals as show below
[.
On Thu, Jun 14, 2018 at 2:40 AM, yixin zhu wrote:
>
>
> On 6/13/2018 6:37 AM, Rob Herring wrote:
>>
>> On Tue, Jun 12, 2018 at 01:40:29PM +0800, Songjun Wu wrote:
>>>
>>> From: Yixin Zhu
>>>
>>> PLL of GRX500 provide clock to DDR, CPU, and peripherals as show below
[...]
>>> +Example:
>>> +
On 6/13/2018 6:37 AM, Rob Herring wrote:
On Tue, Jun 12, 2018 at 01:40:29PM +0800, Songjun Wu wrote:
From: Yixin Zhu
PLL of GRX500 provide clock to DDR, CPU, and peripherals as show below
+-+
|--->| LCPLL3 0|--PCIe clk-->
XO |+-+
On Tue, Jun 12, 2018 at 01:40:29PM +0800, Songjun Wu wrote:
> From: Yixin Zhu
>
> PLL of GRX500 provide clock to DDR, CPU, and peripherals as show below
>
> +-+
> |--->| LCPLL3 0|--PCIe clk-->
>XO |+-+
> +---|
> |+-
From: Yixin Zhu
PLL of GRX500 provide clock to DDR, CPU, and peripherals as show below
+-+
|--->| LCPLL3 0|--PCIe clk-->
XO |+-+
+---|
|+-+
||3|--PAE clk-->
|--->| PLL0B
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