On 2018-07-23 12:12, Peter De Schrijver wrote:
On Mon, Jul 23, 2018 at 10:32:58AM +0100, Ben Dooks wrote:
On 2018-07-23 09:50, Peter De Schrijver wrote:
>On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote:
>>The host1x clock according to both tegra2 and tegra3 manuals is
>>an 8bit di
On Mon, Jul 23, 2018 at 10:32:58AM +0100, Ben Dooks wrote:
>
>
> On 2018-07-23 09:50, Peter De Schrijver wrote:
> >On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote:
> >>The host1x clock according to both tegra2 and tegra3 manuals is
> >>an 8bit divider with lsb being fractional. This is
On 2018-07-23 09:50, Peter De Schrijver wrote:
On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote:
The host1x clock according to both tegra2 and tegra3 manuals is
an 8bit divider with lsb being fractional. This is running into
an issue where the host1x is being set on a tegra20a system
On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote:
> The host1x clock according to both tegra2 and tegra3 manuals is
> an 8bit divider with lsb being fractional. This is running into
> an issue where the host1x is being set on a tegra20a system to
> 266.4MHz but ends up at 222MHz instead.
>
The host1x clock according to both tegra2 and tegra3 manuals is
an 8bit divider with lsb being fractional. This is running into
an issue where the host1x is being set on a tegra20a system to
266.4MHz but ends up at 222MHz instead.
Signed-off-by: Ben Dooks
---
drivers/clk/tegra/clk-tegra-periph.c
5 matches
Mail list logo