On 09/17/2014 06:40 PM, Andrew Bresticker wrote:
On Wed, Sep 17, 2014 at 2:50 AM, Qais Yousef wrote:
On 09/16/2014 12:51 AM, Andrew Bresticker wrote:
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC
local watchdog and count/compare timer. The remainder are CPU
interrupts which
On Wed, Sep 17, 2014 at 10:40 AM, Andrew Bresticker
wrote:
> On Wed, Sep 17, 2014 at 2:50 AM, Qais Yousef wrote:
>> On 09/16/2014 12:51 AM, Andrew Bresticker wrote:
>>>
>>> The MIPS GIC supports 7 local interrupts, 2 of which are the GIC
>>> local watchdog and count/compare timer. The remainder
On Wed, Sep 17, 2014 at 2:50 AM, Qais Yousef wrote:
> On 09/16/2014 12:51 AM, Andrew Bresticker wrote:
>>
>> The MIPS GIC supports 7 local interrupts, 2 of which are the GIC
>> local watchdog and count/compare timer. The remainder are CPU
>> interrupts which may optionally be re-routed through th
On 09/16/2014 12:51 AM, Andrew Bresticker wrote:
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC
local watchdog and count/compare timer. The remainder are CPU
interrupts which may optionally be re-routed through the GIC.
GIC hardware IRQs 0-6 are now used for local interrupts wh
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC
local watchdog and count/compare timer. The remainder are CPU
interrupts which may optionally be re-routed through the GIC.
GIC hardware IRQs 0-6 are now used for local interrupts while
hardware IRQs 7+ are used for external (shared)
5 matches
Mail list logo