Including one for programming the BCH sequence, taking care not to
program two registers marked 'reserved' in the NANDi specification.
Failing to take this precaution results in an imprecise data exception
on ARM platforms. We also add an operation which waits on a completion
timeout (released by the IRQ handler).
Signed-off-by: Lee Jones <lee.jo...@linaro.org>
---
drivers/mtd/nand/stm_nand_bch.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/mtd/nand/stm_nand_bch.c b/drivers/mtd/nand/stm_nand_bch.c
index 5be7889..40767b8 100644
--- a/drivers/mtd/nand/stm_nand_bch.c
+++ b/drivers/mtd/nand/stm_nand_bch.c
@@ -431,6 +431,34 @@ static void nandi_disable_interrupts(struct
nandi_controller *nandi,
}
/*
+ * BCH Operations
+ */
+static inline void bch_load_prog_cpu(struct nandi_controller *nandi,
+ struct bch_prog *prog)
+{
+ uint32_t *src = (uint32_t *)prog;
+ uint32_t *dst = (uint32_t *)(nandi->base + NANDBCH_ADDRESS_REG_1);
+ int i;
+
+ for (i = 0; i < 16; i++) {
+ /* Skip registers marked as "reserved" */
+ if (i != 11 && i != 14)
+ writel(*src, dst);
+ dst++;
+ src++;
+ }
+}
+
+static void bch_wait_seq(struct nandi_controller *nandi)
+{
+ int ret;
+
+ ret = wait_for_completion_timeout(&nandi->seq_completed, HZ/2);
+ if (!ret)
+ dev_err(nandi->dev, "BCH Seq timeout\n");
+}
+
+/*
* Initialisation
*/
static int bch_check_compatibility(struct nandi_controller *nandi,
--
1.8.3.2
--
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