Re: [PATCH 3/3] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

Hello Stephen, Thanks for the review comments. On 4/6/2018 10:10 PM, Stephen Boyd wrote: Quoting Taniya Das (2018-04-02 03:45:45) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index e89584e..e0c83ba 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -83,6 +8

Re: [PATCH 3/3] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

Quoting Taniya Das (2018-04-02 03:45:45) > diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c > index e89584e..e0c83ba 100644 > --- a/drivers/clk/qcom/gdsc.c > +++ b/drivers/clk/qcom/gdsc.c > @@ -83,6 +88,38 @@ static int gdsc_poll_status(struct gdsc *sc, unsigned int > reg, bool en) >

[PATCH 3/3] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

From: Amit Nischal The default behavior of the GDSC enable/disable sequence is to poll the status bits of either the actual GDSCR or the corresponding HW_CTRL registers. On targets which have support for a CFG_GDSCR register, the status bits might not show the correct state of the GDSC, especial